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1.发明授权公开(公告)号：US06909641B2
公开(公告)日：2005-06-21
申请号：US10706133
申请日：2003-11-12
CPC分类号： G11C29/12005 , G11C16/04 , G11C16/16 , G11C29/12
摘要： A memory device includes an array of flash memory cells organized as a plurality of addressable sectors, control circuitry for controlling operations on the array of flash memory cells, and a plurality of sector tagging blocks, with each sector tagging block being associated with one sector of memory cells. Each sector tagging block is adapted to generate a select signal having a first logic level when its associated sector is addressed. The sector tagging blocks are further adapted to generate a common drain signal having a first logic level when any one of the associated sectors is tagged and addressed and to generate the common drain signal having a second logic level when no addressed associated sector is tagged.
摘要翻译： 一种存储器件包括被组织为多个可寻址扇区的闪存单元阵列，用于控制闪存单元阵列上的操作的控制电路和多个扇区标记块，每个扇区标签块与 记忆细胞 每个扇区标记块适于在其相关联的扇区被寻址时产生具有第一逻辑电平的选择信号。 扇区标记块进一步适于在任何一个相关扇区被标记和寻址时产生具有第一逻辑电平的公共漏极信号，并且当没有寻址的相关扇区被标记时，产生具有第二逻辑电平的公共漏极信号。
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2.发明授权公开(公告)号：US06717862B2
公开(公告)日：2004-04-06
申请号：US10229921
申请日：2002-08-28
IPC分类号： G11C1604
CPC分类号： G11C29/12005 , G11C16/04 , G11C16/16 , G11C29/12
摘要： Methods and apparatus to facilitate erasure of multiple sectors of a memory device without the need for externally-supplied erase potentials are advantageous for device testing. During a scan of sector addresses, sector tagging blocks of a memory device provide an output signal to a write state machine indicating whether the addressed sector is tagged for erasure. The sector tagging blocks facilitate resetting of tags on a global basis and setting of tags on a single, bank-wide and/or global basis. Once initiated, the erase operation proceeds to erase each tagged sector of the memory device in sequence without the need for externally-supplied erase potentials and without the need for further direction of the tester hardware. The methods are particularly useful for erasing all sectors of a memory device or all sectors of one memory bank of the memory device.
摘要翻译： 便于擦除存储器件的多个扇区而不需要外部提供的擦除电位的方法和装置对于器件测试是有利的。 在扇区地址的扫描期间，存储器件的扇区标记块向写入状态机提供指示被寻址扇区是否被标记为擦除的输出信号。 扇区标记块有助于在全球范围内重置标签，并在单个银行范围和/或全局基础上设置标签。 一旦启动，擦除操作继续进行以顺序地擦除存储器件的每个标记扇区，而不需要外部提供的擦除电位，并且不需要测试仪硬件的进一步的方向。 这些方法对于擦除存储器件的所有扇区或存储器件的一个存储器组的所有扇区特别有用。
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公开(公告)号：US20050240851A1
公开(公告)日：2005-10-27
申请号：US11166500
申请日：2005-06-24
IPC分类号： G01R31/28 , G06F9/00 , G06F9/24 , G06F11/00 , G06F15/177 , G11C7/00 , G11C17/00 , G11C29/16 , G11C29/48
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
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公开(公告)号：US07318181B2
公开(公告)日：2008-01-08
申请号：US11166500
申请日：2005-06-24
IPC分类号： G11C29/00
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
摘要翻译： 用于在由基于ROM的微控制器管理的编程/擦除操作期间监视存储器件的活动的电路。 可以根据不同的测试模式监控不同的信号。 基于ROM的微控制器由可连接到内部固定频率振荡器或外部时钟源的时钟触发，频率可以从0 Hz变化到应用所需的任何频率。 电路在一系列复用操作中输出状态机状态数据，只读存储器地址和存储器状态信息，以向测试者提供在各种存储器操作期间确定存储器件的状态的能力。
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公开(公告)号：US06977852B2
公开(公告)日：2005-12-20
申请号：US10696973
申请日：2003-10-30
IPC分类号： G01R31/28 , G06F9/00 , G06F9/24 , G06F11/00 , G06F15/177 , G11C7/00 , G11C17/00 , G11C29/16 , G11C29/48
CPC分类号： G11C29/12015 , G11C16/04 , G11C29/16 , G11C29/48 , G11C29/50004
摘要： A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be monitored according to different test modes. The ROM-based microcontroller is triggered by a clock that can be connected to an internal fixed frequency oscillator or to an external clock source for which the frequency can be varied from 0 Hz to any frequency required by the application. The circuit outputs state machine status data, read only memory addresses, and memory status information in a series of multiplexing operations to provide a tester with the ability to determine the state of a memory device during various memory operations.
摘要翻译： 用于在由基于ROM的微控制器管理的编程/擦除操作期间监视存储器件的活动的电路。 可以根据不同的测试模式监控不同的信号。 基于ROM的微控制器由可连接到内部固定频率振荡器或外部时钟源的时钟触发，频率可以从0 Hz变化到应用所需的任何频率。 电路在一系列复用操作中输出状态机状态数据，只读存储器地址和存储器状态信息，以向测试者提供在各种存储器操作期间确定存储器件的状态的能力。
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公开(公告)号：US07277311B2
公开(公告)日：2007-10-02
申请号：US11293760
申请日：2005-12-02
申请人： Giovanni Naso , Giovanni Santin
发明人： Giovanni Naso , Giovanni Santin
IPC分类号： G11C7/00
CPC分类号： G11C29/789 , G11C16/0441 , G11C16/20 , G11C16/26 , G11C17/18
摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.
摘要翻译： 基于单个闪存单元或浮动栅极存储单元的保险丝电路适用于存储器件，特别是在低电压闪速存储器应用中。 熔丝电路包括用于存储数据值的浮动栅存储器单元和用于在通电或根据要求保持和传送浮栅存储单元的数据值的熔丝锁存器。 锁存驱动器电路可以将数据值写入熔丝锁存器而不影响存储在浮动栅极存储单元中的数据值。 熔丝电路可以进一步利用与存储器件的存储器阵列相同的结构，间距，位线组织和字线组织。 由于熔丝电路可以使用相同的结构和组织，因此可以使用与常规存储器阵列相同的数据路径对熔丝电路的数据值进行编程，擦除和读取。
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公开(公告)号：US06845029B2
公开(公告)日：2005-01-18
申请号：US10642959
申请日：2003-08-18
申请人： Giovanni Santin , Giovanni Naso
发明人： Giovanni Santin , Giovanni Naso
CPC分类号： G11C29/789 , G11C16/0441 , G11C16/20 , G11C16/26 , G11C17/18
摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.
摘要翻译： 基于单个闪存单元或浮动栅极存储单元的保险丝电路适用于存储器件，特别是在低电压闪速存储器应用中。 熔丝电路包括用于存储数据值的浮动栅存储器单元和用于在通电或根据要求保持和传送浮栅存储单元的数据值的熔丝锁存器。 锁存驱动器电路可以将数据值写入熔丝锁存器而不影响存储在浮动栅极存储单元中的数据值。 熔丝电路可以进一步利用与存储器件的存储器阵列相同的结构，间距，位线组织和字线组织。 由于熔丝电路可以使用相同的结构和组织，因此可以使用与常规存储器阵列相同的数据路径对熔丝电路的数据值进行编程，擦除和读取。
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公开(公告)号：US5504708A
公开(公告)日：1996-04-02
申请号：US369025
申请日：1995-01-05
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.
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公开(公告)号：US07002828B2
公开(公告)日：2006-02-21
申请号：US10642961
申请日：2003-08-18
申请人： Giovanni Santin , Giovanni Naso
发明人： Giovanni Santin , Giovanni Naso
IPC分类号： G11C17/00
CPC分类号： G11C29/789 , G11C16/0441 , G11C16/20 , G11C16/26 , G11C17/18
摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.
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10.发明授权Flash EEPROM array with P-tank insulated from substrate by deep N-tank 失效闪存EEPROM阵列，带有P型槽，通过深N槽与基板绝缘
公开(公告)号：US5411908A
公开(公告)日：1995-05-02
申请号：US890577
申请日：1992-05-28
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/70
CPC分类号： H01L27/115 , H01L27/11521
摘要： In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.
摘要翻译： 根据本发明的一个实施例，非易失性存储器阵列被封装在P坦克中，并且P坦克封装在深N坦克中，两个坦克将存储器阵列与基板分开，并从另一个电路 集成存储电路。 深N坦克允许对包含存储器阵列的P坦克施加大约-8V的负电压。 应用该负电压允许存储器阵列的单元用具有大约+ 10V的峰值的电压脉冲编程，而不是现有技术存储器阵列的+ 18V峰值。 因为诸如字线驱动器电路的外部电路需要以+10V而不是+ 18V驱动字线，所以本发明允许使用更薄的栅极绝缘体和节省空间的更短的尺寸来构造该外部电路。
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