公开(公告)号：US06946690B1

公开(公告)日：2005-09-20

申请号：US09816287

申请日：2001-03-21

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper

IPC分类号： H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/7436 ,  H01L29/87

摘要： The holding voltage (the minimum voltage required for operation) of a LVTSCR-like device is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by reducing the size of the p+ emitter defined by the LVTSCR-like device. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins, having better current capabilities than a GGNMOS and better holding voltage characteristics than a LVTSCR.

摘要翻译： LVTSCR类器件的保持电压（操作所需的最小电压）增加到大于受保护节点上的直流偏置的值。 通过减小由LVTSCR类器件限定的p +发射极的尺寸来增加保持电压。 因此，可以利用LVTSCR为电源引脚提供ESD保护，具有比GGNMOS更好的电流能力和比LVTSCR更好的保持电压特性。

公开(公告)号：US06894881B1

公开(公告)日：2005-05-17

申请号：US10079336

申请日：2002-02-19

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0255

摘要： In an ESD protection circuit, diodes for shunting current through an ESD clamp include a third terminal in order to provide a dual current path through the diode structure and provide for a voltage drop to the input of the protected internal circuit. In another embodiment, where a bipolar junction transistor is used as an ESD clamp to shunt current to ground between an I/O pad and an input to a protected internal circuit, a lower voltage is provided to the internal circuit by providing a voltage drop across an internal resistive element of the bipolar junction transistor. This is achieved by making use of two base terminals, one connected to the I/O pad, and the other connected to the input of the internal circuit and spaced from the first contact by the base polysilicon region of the bipolar junction transistor.

摘要翻译： 在ESD保护电路中，用于通过ESD钳位电流分流的二极管包括第三端子，以便提供通过二极管结构的双电流路径并且提供对受保护内部电路的输入的电压降。 在另一个实施例中，在将双极结型晶体管用作ESD钳位器以将I / O焊盘和保护的内部电路的输入之间的电流分流到地之间，通过提供一个电压降到内部电路来提供较低的电压 双极结型晶体管的内部电阻元件。 这是通过使用两个基极端子，一个连接到I / O焊盘，另一个连接到内部电路的输入并且与第一触点间隔开双极结型晶体管的基极多晶硅区域来实现。

公开(公告)号：US06841829B1

公开(公告)日：2005-01-11

申请号：US10436559

申请日：2003-05-12

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/732 ,  H01L23/62 ,  H01L29/00

CPC分类号： H01L29/732 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/0821

摘要： In a BSCR and method of making a BSCR, a npn BJT structure is created and a p+ region is provided that is connected to the collector of the BJT, and one or more of the NBL, sinker and n+ collector of the BJT are partially blocked. In this way the NBL is formed into a comb-like NBL with a plurality of tines in one embodiment. The sinker and n+ collector may also be formed into a plurality islands. Furthermore, the period of the tines and islands may be varied to provide the desired BSCR characteristics.

摘要翻译： 在BSCR和制造BSCR的方法中，产生npn BJT结构，并且提供连接到BJT的集电极的p +区域，并且BJT的NBL，沉没器和n +集电极中的一个或多个被部分阻塞 。 以这种方式，在一个实施例中，NBL形成为具有多个尖齿的梳状NBL。 沉降片和n +集电体也可形成多个岛。 此外，可以改变尖齿和岛的周期以提供期望的BSCR特性。

公开(公告)号：US06784029B1

公开(公告)日：2004-08-31

申请号：US10121514

申请日：2002-04-12

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

IPC分类号： H01L218248

CPC分类号： H01L27/0262 ,  H01L27/0623 ,  H01L29/0626 ,  H01L29/0649 ,  H01L29/87

摘要： In a Bi-CMOS ESD protection device, dual voltage capabilities are achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.

摘要翻译： 在Bi-CMOS ESD保护器件中，通过在n型材料中提供两个横向间隔开的p区并且在每个p区中限定n +区和p +区以实现类似的IV特性来实现双电压能力。 对于由SCR装置在正方向上限定的那些，但是在这种情况下，在两个方向具有这些特性。 器件可能是不对称的，以适应正向和负向不同的电压幅度。

公开(公告)号：US06717219B1

公开(公告)日：2004-04-06

申请号：US10121183

申请日：2002-04-12

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

IPC分类号： H01L2362

CPC分类号： H01L29/7436 ,  H01L27/0259

摘要： In a Bi-CM0S ESD protection structure, the holding voltage is increased by a desired amount by including a NBL of chosen length. The positioning of the NBL may be adjusted to adjust the I-V characteristics of the structure. Dual voltage capabilities may be achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region in each of the p-regions to define I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. Over and above the NBL position being adjusted relative to the p-regions, the two p-regions may vary in doping level, and dimensions to achieve different I-V characteristics for the device in the positive and negative directions.

摘要翻译： 在Bi-CM0S ESD保护结构中，通过包括选定长度的NBL，保持电压增加所需量。 可以调整NBL的定位以调整结构的I-V特性。 可以通过在n材料中提供两个横向间隔的p区并且在每个p区中限定n +区和p +区来限定IV特性来实现双电压能力，其类似于由SCR器件中定义的那些 正方向，但是在这种情况下，在两个方向都具有这些特征。 在相对于p区域调整NBL位置之上和之上时，两个p区可以在掺杂水平和尺寸上变化，以在正向和负向方向上实现器件的不同I-V特性。

公开(公告)号：US06690069B1

公开(公告)日：2004-02-10

申请号：US10210941

申请日：2002-08-02

申请人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

发明人： Vladislav Vashchenko ,  Ann Concannon ,  Peter J. Hopper ,  Marcel ter Beek

IPC分类号： H01L2362

CPC分类号： H01L27/0262

摘要： In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.

摘要翻译： 在使用SCR类结构的ESD保护器件中，提供了高度鲁棒的垂直器件，并且容易地允许在制造期间调节触发电压。 此外，它可以基于PNP和NPN BJT结构的互补形式实现，以提供正和负脉冲保护。

公开(公告)号：US06433368B1

公开(公告)日：2002-08-13

申请号：US09768033

申请日：2001-01-22

申请人： Vladislav Vashchenko ,  Peter J. Hopper

发明人： Vladislav Vashchenko ,  Peter J. Hopper

IPC分类号： H01L2974

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： The holding voltage (the minimum voltage required for operation) of a low-voltage triggering silicon-controlled rectifier (LVTSCR) is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by inserting a voltage drop between the to-be-protected node and the emitter of the pnp transistor of the LVTSCR. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins.

摘要翻译： 低压触发硅控整流器（LVTSCR）的保持电压（操作所需的最小电压）增加到大于被保护节点上的直流偏置的值。 通过在受保护节点和LVTSCR的pnp晶体管的发射极之间插入电压降来增加保持电压。 因此，LVTSCR可用于为电源引脚提供ESD保护。

公开(公告)号：US06355959B1

公开(公告)日：2002-03-12

申请号：US09658743

申请日：2000-09-11

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Manuel Carneiro

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Manuel Carneiro

IPC分类号： H01L2701

CPC分类号： H01L27/0266

摘要： An ESD protection structure for use with ICs that can protect from ESD events of both positive and negative polarities, has a low snapback holding voltage and a high maximum snapback current, and is relatively immune to thermal overheating. The structure includes a semiconductor substrate of a first conductivity type (typically P-type), as well as first and second well regions of a second conductivity type (typically N-type) that are separated a gap region of the first conductivity type and disposed in the substrate. A gate silicon dioxide layer overlies the gap region and a gate electrode overlies the gate silicon dioxide layer. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The structure further includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. Also included are first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. During operation, the structure undergoes low current avalanche breakdown of the gap region between the first and second floating regions, followed by “double injection” of both holes and electrons. The structure's symmetrical nature provides for protection from both positive and negative ESD events and the gate electrode provides breakdown control capability.

摘要翻译： 与可以防止正极性和负极性ESD事件的IC一起使用的ESD保护结构具有低的恢复保持电压和高的最大回跳电流，并且相对地不受热过热。 该结构包括第一导电类型（通常为P型）的半导体衬底以及第二导电类型（通常为N型）的第一和第二阱区，其分隔第一导电类型的间隙区域并且被布置 在基材中。 栅极二氧化硅层覆盖在间隙区域上，栅电极覆盖栅极二氧化硅层。 还包括设置在与间隙区域相邻的第一和第二阱区域中的第一和第二浮动区域（第二导电类型）。 该结构还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区间隔开的第一导电类型的第一和第二接触区域。 还包括分别设置在第一和第二阱区上并分别与第一和第二浮动区间隔开的第二导电类型的第一和第二接触区域。 在操作期间，该结构经历第一和第二浮动区之间的间隙区域的低电流雪崩击穿，随后是空穴和电子的“双重注入”。 该结构的对称性质提供了正，负ESD事件的保护，栅电极提供击穿控制能力。

公开(公告)号：US08303484B2

公开(公告)日：2012-11-06

申请号：US12621719

申请日：2009-11-19

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  William French ,  Visvamohan Yegnashankaran

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  William French ,  Visvamohan Yegnashankaran

IPC分类号： A61B1/00

CPC分类号： A61B1/041 ,  A61B1/00082 ,  A61B1/00156 ,  A61B1/005 ,  A61B1/31 ,  A61B8/12 ,  A61B8/429 ,  A61B8/4472

摘要： A self-propelled robotic device moves through bodily and other passageways by inflating regions of an overlying bladder along the length of the robotic device in a sequence that imparts motion to the device. The regions of the overlying bladder are inflated by energizing a plurality of coils, which are surrounded by a ferrofluid, in a sequence. The ferrofluid responds to the magnetic field created by an energized coil by creating a bulge in the side wall of the overlying bladder.

摘要翻译： 自动推进的机器人装置通过身体和其他通道沿着机器人装置的长度沿着向装置施加运动的顺序使覆盖的膀胱的区域膨胀而移动。 通过对由铁磁流体包围的多个线圈进行顺序地激励上覆的气囊的区域来充气。 铁磁流体通过在上覆气囊的侧壁中产生凸起来响应由通电线圈产生的磁场。

公开(公告)号：US07233521B1

公开(公告)日：2007-06-19

申请号：US11078761

申请日：2005-03-11

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashshenco ,  Philipp Lindorfer

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashshenco ,  Philipp Lindorfer

IPC分类号： G11C11/34

CPC分类号： G11C27/005 ,  G11C11/5621 ,  G11C16/0441 ,  G11C16/10

摘要： A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.

摘要翻译： 一种能够接收模拟信号并将其存储为数字信号的存储装置。 存储装置包括被配置为接收模拟输入电压的输入节点和两个非易失性存储单元。 第二非易失性存储单元被耦合以从输入节点接收模拟输入信号。 第二非易失性存储单元能够被编程为多个编程状态之一。 耦合到第二非易失性存储单元的第一非易失性存储单元也能够被编程为多个编程状态之一。 在操作期间，第二非易失性存储器单元和第一非易失性存储器单元都被编程为指示模拟输入电压的大小的选择的第二编程状态。 第一编程状态和第二编程状态一起表示与模拟输入电压的大小相称的数字值。