公开(公告)号：US10890961B2

公开(公告)日：2021-01-12

申请号：US14315889

申请日：2014-06-26

Applicant: Microchip Technology Incorporated

Inventor： Craig L. King ,  Adrian-Nicolae Toader

IPC: G06F1/32 ,  G06F1/3206 ,  G01R31/40 ,  G01R35/00 ,  G01R21/133 ,  H02M1/42

Abstract: A power monitor is used to estimate the amount of input power that is supplied to a power supply. The power monitor is protected by an EMI filter within the power supply. The power monitor measures a line frequency and a line voltage within the power supply and it also retrieves empirically derived coefficient values from memory where the coefficient values are used in formulas that have been determined to model the non-linear behavior of voltage and current in the power supply. The formulas are used to estimate the discrepancy between input power to the power supply and observed power values at a power monitor. The formulas used by the power monitor calculate power compensation factors based on the measured line frequency, the measured line voltage and the retrieved formula coefficient values. The power compensation factors are used to estimate the input power supplied to the power supply.

公开(公告)号：US20200373938A1

公开(公告)日：2020-11-26

申请号：US16879917

申请日：2020-05-21

Applicant: Microchip Technology Incorporated

Inventor： Vincent Quiquempoix ,  Zeynep Sueda Turk

IPC: H03M1/46 ,  H03M1/10 ,  H03M1/12

Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.

公开(公告)号：US20200328115A1

公开(公告)日：2020-10-15

申请号：US16450391

申请日：2019-06-24

Applicant: Microchip Technology Incorporated

Inventor： Paul Fest

IPC: H01L21/768 ,  H01L49/02 ,  H01L21/311

Abstract: A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) including IC elements, e.g., memory components. A first contact etch stop layer is formed over the IC elements. A TFR layer stack including a TFR etch stop layer, a TFR film layer, and a second contact etch stop layer is formed over the first contact etch stop layer, and in some cases over one or more pre-metal dielectric layers. A patterned mask is formed over the IC stack, and the stack is etched, through both the first and second contact etch stop layers, to simultaneously form (a) first contact openings exposing contact regions of the IC elements and (b) second contact opening(s) exposing the TFR film layer. The first and second contact openings are filled with conductive material to form conductive contacts to the IC elements and the TFR film layer.

公开(公告)号：US10784766B2

公开(公告)日：2020-09-22

申请号：US16428094

申请日：2019-05-31

Applicant: Microchip Technology Incorporated

Inventor： Santosh Manjunath Bhandarkar ,  Alex Dumais

IPC: H02M1/08 ,  H03K5/24 ,  H02M3/157

Abstract: Adaptive slope compensation for current mode control in a switch mode power supply converter is computed for every switching cycle based upon the input voltage and duty-cycle whereby the quality factor is maintained at a constant value. A digital signal processing (DSP) capable microcontroller comprises a voltage loop compensator and generates a desired current reference for every switching cycle. Slope calculations are adapted for switching frequency, inductance value, current circuit gain, etc. The slope calculation result is applied to a pulse-digital-modulation (PDM) digital-to-analog converter (DAC) capable of changing its output levels at a very fast rate compared to the power supply switching frequency whereby the required current slope is provided within the switching period. Actual inductor current may be used to compare against the slope reference, thereby taking care of changes in the inductance values under load. The slope levels are automatically changed when the switching frequency is changed.

公开(公告)号：US10749994B2

公开(公告)日：2020-08-18

申请号：US15786224

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Hariramanathan Ramakrishnan ,  Bryan A. Whitehead ,  Maksim A. Azarov ,  Neil A. Winchester ,  William R. Chiechi

IPC: H04L29/06 ,  H04L12/861 ,  G06F15/16 ,  G06F15/163 ,  H04N21/239 ,  H04N21/41 ,  H04L29/12

Abstract: A network device (ND) includes a first interface controller operable to transfer data between the ND and a host processing unit (host), a second interface controller operable to transfer data between the ND and the host, a network interface configured to interface the ND with a network, and a control unit operable to: receive incoming data from the network, process the incoming data, and transmit the processed incoming data to the host through the second interface controller; or, receive outgoing data from the host through the second interface controller, process the received outgoing data, and transmit the processed outgoing data to the network. The first interface controller, the control unit, and the network interface are together operable to enable the host to transmit and/or receive other data to and/or from the network and the first interface controller. The host and the control unit share a same network address.

公开(公告)号：US10741507B2

公开(公告)日：2020-08-11

申请号：US15891775

申请日：2018-02-08

Applicant: Microchip Technology Incorporated

Inventor： Behrooz Mehr ,  Fernando Chen ,  Emmanuel de los Santos ,  Alex Kungo

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L23/482 ,  H01L23/552

Abstract: Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be electrically connected to ground by wire bonds extending to the substrate.

公开(公告)号：US10734902B2

公开(公告)日：2020-08-04

申请号：US16564221

申请日：2019-09-09

Applicant: Microchip Technology Incorporated

Inventor： Jiong Ou ,  Scott Dearborn

IPC: H02M3/158 ,  G05F1/45 ,  H02M1/08 ,  H02M1/00

Abstract: A power converter includes a buck leg circuit connected between a voltage input of the power converter and ground, a boost leg circuit connected between a voltage output of the power converter and ground, an inductor connected between the buck leg circuit and the boost leg circuit, an error amplifier configured to compare the voltage output of the power converter against a reference voltage to yield a feedback signal, and a control circuit. The control circuit is configured to generate a reference buck ramp configured to be compared against the feedback signal to determine whether to operate the buck leg circuit in buck mode, and to generate a reference boost ramp by superposing a variable boost ramp portion on to the reference buck ramp, the reference boost ramp configured to be compared against the feedback signal to determine whether to operate the boost leg circuit in boost mode.

公开(公告)号：US10734298B2

公开(公告)日：2020-08-04

申请号：US16121313

申请日：2018-09-04

Applicant: Microchip Technology Incorporated

Inventor： Hyunsoo Yeom ,  Ajay Kumar ,  John House

IPC: H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H03K4/00

Abstract: Methods of making a semiconductor device packages may involve placing a metal material at least partially around a region of integrated circuitry embedded within an active surface of a semiconductor die, the metal material located on the active surface. At least a portion of the metal material may be left electrically disconnected from the region of integrated circuitry. The semiconductor die and the metal material may be encapsulated in an encapsulant material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.

公开(公告)号：US10727735B2

公开(公告)日：2020-07-28

申请号：US16051872

申请日：2018-08-01

Applicant: Microchip Technology Incorporated

Inventor： Santosh Manjunath Bhandarkar ,  Alex Dumais

IPC: H02M3/158 ,  H02M1/42 ,  H03K17/13

Abstract: A circuit arrangement, signal processor, and method for interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; and a signal processor. The signal processor is connected to the controllable switching devices and comprises at least a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices The signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce the zero-crossing time.

公开(公告)号：US10725961B2

公开(公告)日：2020-07-28

申请号：US16371880

申请日：2019-04-01

Applicant: Microchip Technology Incorporated

Inventor： Morten Werner Lund ,  Lloyd Clark ,  Odd Magne Reitan

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F9/54 ,  G06F13/362 ,  G06F3/041 ,  G09G5/00

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.