-
公开(公告)号：US11494324B2
公开(公告)日：2022-11-08
申请号：US16998097
申请日：2020-08-20
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Yann Johner
Abstract: An apparatus such as a node in a daisy chain of electronic devices includes a serial data input port receive input from an electronic device in the daisy chain. The apparatus includes a serial data output port to send output to another electronic device in the daisy chain. The apparatus includes a chip select input port configured to receive input from a master control unit, and an interface circuit configured to, in a daisy chain streaming mode, and based on a received command and changed edge of a signal on the chip select input port, repeatedly: read data from a data source of the apparatus to yield data, output the data to the serial data output port, and copy other data received at the serial data input port to the serial data output port after the data.
-
2.发明申请公开(公告)号：US20200373938A1
公开(公告)日：2020-11-26
申请号：US16879917
申请日：2020-05-21
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Zeynep Sueda Turk
Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.
-
公开(公告)号：US09496887B1
公开(公告)日：2016-11-15
申请号：US14710105
申请日：2015-05-12
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Alexandre Barreto
CPC classification number: H03M1/34 , G06F1/3203 , G06F1/325 , G06F3/05 , H03M1/001 , H03M1/002 , H03M1/12 , H03M1/1245
Abstract: An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.
Abstract translation: 模数转换器包括用于接收模拟输入并将输入转换成数字信号的电路; 以及非瞬态控制电路，被配置为：接收采样时间; 接收转换时间; 从至少一个睡眠模式确定上电时间; 并且如果上电时间和转换时间之和小于采样时间，则使数模转换器进入至少一个休眠模式。
-
公开(公告)号：US20160282391A1
公开(公告)日：2016-09-29
申请号：US14669232
申请日：2015-03-26
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Michael Brumann
IPC: G01R21/00 , G01R23/165 , H03L7/099 , H03M1/12 , H03M1/36
CPC classification number: G01R21/003 , G01R21/06 , G01R21/1331 , G01R23/165 , H03L7/099 , H03M1/1245 , H03M1/36
Abstract: A power metering circuit includes a current input path for receiving an analog current input at a first analog to digital converter; a voltage input path for receiving an analog voltage input at a second analog to digital converter; a multiplier configured to multiply an output of the current input path and the voltage input path; a notch filter configured to receive an output of the multiplier, the notch filter having a stop band based on a line frequency; and a control circuit for setting a sampling frequency of the first analog to digital converter and the second analog to digital converter to a multiple of the line frequency.
Abstract translation: 电力计量电路包括用于在第一模数转换器处接收模拟电流输入的电流输入路径; 用于接收在第二模数转换器处输入的模拟电压的电压输入路径; 配置为乘以当前输入路径的输出和电压输入路径的乘法器; 陷波滤波器，被配置为接收所述乘法器的输出，所述陷波滤波器具有基于线路频率的阻带; 以及控制电路，用于将第一模数转换器和第二模数转换器的采样频率设置为线路频率的倍数。
-
公开(公告)号：US09300319B2
公开(公告)日：2016-03-29
申请号：US14874729
申请日：2015-10-05
Applicant: MICROCHIP TECHNOLOGY INCORPORATED
Inventor： Vincent Quiquempoix
CPC classification number: H03M3/34 , H03K5/15 , H03M1/00 , H03M1/12 , H03M1/804 , H03M3/30 , H03M3/322 , H03M3/356 , H03M3/422
Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.
-
Patent Agency Ranking
公开(公告)号：US09154155B2
公开(公告)日：2015-10-06
申请号：US14181904
申请日：2014-02-17
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
CPC classification number: H03M3/34 , H03K5/15 , H03M1/00 , H03M1/12 , H03M1/804 , H03M3/30 , H03M3/322 , H03M3/356 , H03M3/422
Abstract: An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.
Abstract translation: 用于开关电容器模拟 - 数字转换器的输入级具有接收输入电压的差分电压输入端，接收斩波参考电压的差分参考电压输入，公共电压连接和差分输出。 一对输入电容器耦合在差分电压输入和差分输出之间，一对参考电容耦合在差分参考电压输入端之间。 开关单元由在第一阶段期间可操作的第一和第二相控制，以将输入电容器的第一端与公共电压连接相连，并将参考电容器的第一端与反相的差分电压基准耦合; 以及在第二阶段期间将输入电容器的第一端与差分输入电压连接，并将参考电容器的第一端与非反相差分电压基准耦合。
-
公开(公告)号：US20140253355A1
公开(公告)日：2014-09-11
申请号：US14202823
申请日：2014-03-10
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
CPC classification number: H03M1/802 , H03M1/0665 , H03M3/30 , H03M3/424 , H03M3/464
Abstract: A digital-to analog converter (DAC) of the charge transfer type for use in a sigma delta modulator, includes a capacitor switch unit operable to generate a 4n+1 output levels, comprising: a plurality of second switching units for coupling first terminals of a plurality of reference capacitor pairs with either a positive or a negative reference signal; wherein the second terminals of the plurality of reference capacitor pairs are coupled in parallel, respectively; wherein for even transfers a single switching combination is provided to achieve linearity and wherein for odd transfers an average of different switching combinations is provided to achieve linearity; wherein an even transfer is when an input of the DAC is even and an odd transfer is when an input to the DAC is odd.
Abstract translation: 一种用于Σ-Δ调制器的电荷转移型数模转换器（DAC）包括一个可操作以产生4n + 1输出电平的电容器开关单元，包括：多个第二开关单元，用于将第 具有正或负参考信号的多个参考电容器对; 其中所述多个参考电容器对中的第二端子分别并联耦合; 其中，对于偶数传输，提供单个切换组合以实现线性，并且其中对于奇数传输，提供不同切换组合的平均值以实现线性度; 其中偶数传输是当DAC的输入是偶数时，并且奇数传输是当DAC的输入是奇数时。
-
公开(公告)号：US12278652B2
公开(公告)日：2025-04-15
申请号：US18129991
申请日：2023-04-03
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
IPC: H03M3/00
Abstract: A device and method for sigma-delta modulation may include an input signal and a plurality of integrators. The output of the integrators and a data input may be input to an adder, the sum output to be input to a quantizer to generate a quantized output signal. A reset input to the first integrator may be asserted during a first sample of the quantized output signal to reduce the signal discontinuity at the input of the first integrator, which improves the stability of the sigma-delta modulator.
-
公开(公告)号：US11221977B2
公开(公告)日：2022-01-11
申请号：US16998050
申请日：2020-08-20
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix
Abstract: A node in a daisy chain includes a serial data input port configured to receive input from an electronic device, a serial data output port configured to send output to another electronic device, a chip select input port configured to receive input from a master control unit, a timer, and an interface circuit. The interface circuit may be configured to, in a daisy chain mode, copy data received at the serial data input port to the serial data output port, and upon receipt of a changed edge of a chip select signal on the chip select input port, initiate the timer. The interface circuit may be configured to, upon the completion of a time to be determined by the timer, enter the daisy chain mode.
-
公开(公告)号：US20210064555A1
公开(公告)日：2021-03-04
申请号：US16998170
申请日：2020-08-20
Applicant: Microchip Technology Incorporated
Inventor： Vincent Quiquempoix , Yann Johner
Abstract: An apparatus may include a serial data output port configured to send output data to a electronic device. The apparatus may include a serial data input port configured to receive input data from another electronic device. The apparatus may include a chip select output port configured to send output to the electronic devices connected in a daisy chain. The apparatus may include a interface circuit, configured to determine that a given electronic device is to selectively execute a first command. The interface circuit may be further configured to issue a complex command to the electronic devices connected. The complex command may indicate to the f electronic devices that additional commands are to be selectively executed.
-
-
-
-
-
-
-
-
-
Search Results
35
records
(took 0.017 seconds)
