QUANTUM KARNAUGH MAP
    131.
    发明申请
    QUANTUM KARNAUGH MAP 审中-公开
    量子卡拉图地图

    公开(公告)号:US20140157214A1

    公开(公告)日:2014-06-05

    申请号:US14173422

    申请日:2014-02-05

    Inventor: Doyeol AHN

    CPC classification number: G06F17/5022 B82Y10/00 G06N99/002

    Abstract: Techniques for determining and a computing device configured to determine a quantum Karnaugh map through decomposing a quantum circuit into a multiple number of sub-circuits are provided. Also, techniques for obtaining and a computing device configured to obtain a quantum circuit which includes the minimum number of gates among possible quantum circuits corresponding to a quantum Karnaugh map are also provided.

    Abstract translation: 提供了用于确定的技术和被配置为通过将量子电路分解成多个子电路来确定量子卡诺图的计算装置。 此外,还提供了用于获得和计算装置的技术,其被配置为获得包括对应于量子卡诺图的可能量子电路中的最小数量的栅极的量子电路。

    Textile triboelectric nanogenerators with diverse 3D-spacer fabrics for improved output voltage

    公开(公告)号:US12267026B2

    公开(公告)日:2025-04-01

    申请号:US18090028

    申请日:2022-12-28

    Inventor: Hyeok Kim

    Abstract: A triboelectric nanogenerator (TENG) using a 3D-spacer fabric and polydimethylsiloxane (PDMS) shows great application potential for biokinetic energy harvesting and a multifunctional self-power device. In the present disclosure, a TENG with a fabric-PDMS-fabric structure is fabricated using diverse three-dimensional (3D) fabrics and PDMS. Peak-to-peak output voltages of the diverse 3D-spacer fabrics are compared. The output voltages are changed due to structures and vertical fibers. In addition, a coefficient of surface friction between PDMS and fabric improves the output voltage. TENGs using different 3D-spacer polymeric fabrics show different maximum peak-to-peak output voltage performances. This is due to the stiffness, lateral elasticity, and 3D morphology of the fabrics. It is considered that those factors including the stiffness, the lateral elasticity, and the 3D morphology influence the densities in vertical and lateral fiber-to-fiber interaction.

    Importance of architectural asymmetry for improved triboelectric nanogenerators with 3D spacer fabrics

    公开(公告)号:US12107517B2

    公开(公告)日:2024-10-01

    申请号:US18092155

    申请日:2022-12-30

    Inventor: Hyeok Kim

    CPC classification number: H02N1/04

    Abstract: The importance of architectural asymmetry is investigated to improve the output voltage of TENGs with polyester/spandex blend three-dimensional (3D) spacer fabrics. Different types of TENGs are fabricated by stacking the 3D spacer fabrics, polydimethylsiloxane (PDMS) films, and electrodes with different stack configurations. The 3D spacer fabric TENGs fabricated with higher architectural asymmetry show higher output voltages than those fabricated with lower architectural asymmetry. In particular, the TENG with the PDMS/fabric/fabric configuration shows the highest peak-to-peak output voltage among all types. An increase in the TENG output voltage is attributed to the relatively high architectural asymmetry in the device configuration and the relatively high effective density of triboelectric charge.

    Highly efficient inverted polymer solar cells using an indium gallium zinc oxide interfacial layer

    公开(公告)号:US12101950B2

    公开(公告)日:2024-09-24

    申请号:US18089844

    申请日:2022-12-28

    Inventor: Hyeok Kim

    Abstract: Organic polymer semiconductor-based polymer solar cells (PSCs) have attracted considerable research interest due to having excellent electrical, structural, optical, mechanical, and chemical properties. In the past 20 years, considerable efforts have been made to develop PSCs. Generally, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) is used as a hole transport layer (HTL) of the PSC to enhance hole extraction efficiency, but highly acidic PEDOT:PSS destroys an indium tin oxide (ITO) electrode and an active layer and thus reduces the lifetime of the device. To avoid this problem, some attempts have been made to develop inverted PSCs having different electron transport layers (ETLs). However, such a device has limited power conversion efficiency (PCE) due to low electron mobility of the ETL. Therefore, attempts have been made to enhance the PCE of inverted PSCs using indium gallium zinc oxide (IGZO) having optimized indium (In), gallium (Ga), and zinc (Zn) contents. Accordingly, inverted PSCs that have ZnO or IGZO (having varying In:Ga:Zn molar ratios) as an ETL and have an ITO/ETL/PTB7:PC71BM/MoO3/Al structure have been constructed. The PCE of the inverted PSC can be increased from 6.22% to 8.72% using IGZO having an optimized weight ratio of In, Ga, and Zn.

    QUANTUM FOURIER TRANSFORMATION CIRCUIT AND METHOD OF FORMING THE SAME

    公开(公告)号:US20240193458A1

    公开(公告)日:2024-06-13

    申请号:US18090223

    申请日:2022-12-28

    Inventor: Do Yeol AHN

    CPC classification number: G06N10/60 G06N10/20 G06N10/70

    Abstract: The present invention discloses a Quantum Fourier Transformation (QFT) circuit and a method of forming the QFT circuit capable of reducing the number of T-count and T-depth. The method of forming a QFT circuit comprises moving Hadamard gate (H-gate) of an even-numbered qubits to the earliest stage where there is no quantum entanglement with other qubits, in a standard n (n is a natural number greater than or equal to 5) qubit QFT, decomposing quantum circuit into a form in which Rz gate is implemented, using quantum addition, and reducing a number of Rz gate layers using ancilla qubits.

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