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    I/O cell configuration for multiple I/O standards
    131.
    发明授权
    I/O cell configuration for multiple I/O standards 有权
    多个I / O标准的I / O单元配置

    公开(公告)号：US06836151B1

    公开(公告)日：2004-12-28

    申请号：US10781334

    申请日：2004-02-17

    申请人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

    发明人： Cameron McClintock ,  Richard G. Cliff ,  Bonnie I. Wang

    IPC分类号： H03K190195

    CPC分类号： H03K19/018585

    摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

    摘要翻译： 提供电路以单独配置集成电路的每个I / O以与不同的LVTTL I / O标准兼容。 这可以通过仅一个I / O电源电压完成，其中该电压是特定应用中所需的I / O电压中最高的。 电路通过调节I / O单元的输出电压进行操作，使其高于VOH并低于其符合的LVTTL标准的最大VIH。 由于每个I / O单元都可单独配置，任何I / O都可以驱动到任何LVTTL规范。

    Programmable logic device with hierarchical interconnection resources
    132.
    发明授权
    Programmable logic device with hierarchical interconnection resources 失效
    具有分层互连资源的可编程逻辑器件

    公开(公告)号：US06798242B2

    公开(公告)日：2004-09-28

    申请号：US10426991

    申请日：2003-04-29

    申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

    Programmable logic device with hierarchical interconnection resources
    134.
    发明授权
    Programmable logic device with hierarchical interconnection resources 有权
    具有分层互连资源的可编程逻辑器件

    公开(公告)号：US06577160B2

    公开(公告)日：2003-06-10

    申请号：US10170026

    申请日：2002-06-10

    申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联。 本地导体与每个区域相关联。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

    Logic element for a programmable logic integrated circuit
    135.
    发明授权
    Logic element for a programmable logic integrated circuit 有权
    可编程逻辑集成电路的逻辑元件

    公开(公告)号：US06359469B1

    公开(公告)日：2002-03-19

    申请号：US09916402

    申请日：2001-07-26

    申请人： David W. Mendel ,  Richard G. Cliff

    发明人： David W. Mendel ,  Richard G. Cliff

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A logic element (300) for a programmable logic integrated circuit allows two independent logic functions to be carried out during the same clock cycle. In an embodiment, a 4-input lookup table (406) is provided using a 3-input lookup table (434) and two 2-input lookup tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic integrated circuit.

    摘要翻译： 用于可编程逻辑集成电路的逻辑元件（300）允许在相同时钟周期内执行两个独立的逻辑功能。 在一个实施例中，使用3输入查找表（434）和两个2输入查找表来提供4输入查找表（406）。 可以从逻辑元件同时路由4输入查找表（406）和3输入查找表（434）的结果。 它还允许在执行独立的逻辑功能的同时通过逻辑元件（300）路由信号。 提供进位逻辑（425）。 进位逻辑（486）的结果可以被路由到可编程逻辑集成电路的全局和局部互连结构。

    Programmable logic device with hierarchical interconnection resources
    136.
    发明授权
    Programmable logic device with hierarchical interconnection resources 有权
    具有分层互连资源的可编程逻辑器件

    公开(公告)号：US06300794B1

    公开(公告)日：2001-10-09

    申请号：US09488025

    申请日：2000-01-20

    申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

    Programmable logic with on-chip DLL or PLL to distribute clock
    137.
    发明授权
    Programmable logic with on-chip DLL or PLL to distribute clock 有权
    具有片内DLL或PLL的可编程逻辑来分配时钟

    公开(公告)号：US06292016B1

    公开(公告)日：2001-09-18

    申请号：US09588034

    申请日：2000-06-05

    申请人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    发明人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： G03F738

    CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17732 ,  H03L7/0814 ,  H03L7/087

    摘要： A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

    摘要翻译： 可编程逻辑器件或现场可编程门阵列包括片上时钟同步电路以同步参考或系统时钟信号。 时钟同步电路是一个实现中的延迟锁定环（DLL）电路和另一个实现中的锁相环（PLL）电路。 DLL或PLL电路可以是模拟或数字的。 时钟同步电路产生分布在整个可编程集成电路中的同步时钟信号。 同步时钟信号可编程地连接到集成电路的可编程逻辑元件或逻辑阵列块（LAB）。 当在集成电路内分配时钟信号时，时钟同步电路减小或最小化时钟偏移。 时钟同步电路提高了可编程逻辑集成电路的整体性能。

    Programmable logic device with enhanced multiplexing capabilities in interconnect resources
    138.
    发明授权
    Programmable logic device with enhanced multiplexing capabilities in interconnect resources 有权
    具有增强的互连资源复用能力的可编程逻辑器件

    公开(公告)号：US06278288B1

    公开(公告)日：2001-08-21

    申请号：US09574371

    申请日：2000-05-19

    申请人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

    发明人： Andy L. Lee ,  Richard G. Cliff ,  David Jefferson ,  Cameron McClintock ,  Kurosu R. Altaf

    IPC分类号： G06F738

    CPC分类号： H03K19/17752 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1778

    摘要： A programmable logic integrated circuit device is provided with enhanced capability for dynamically multiplexing signals on the device. Controllable connectors that are provided on the device for connecting any of several connector input signals to a connector output are controlled by control signals that can be programmable selected to be either constant or variable signals. If a control signal is selected to be a variable signal, then the connector controlled by that control signal can be operated as a dynamic multiplexer of the input signals to that connector. The controllable connectors may advantageously be used as the connectors that are employed for allowing several possible signal sources to effectively share a smaller of number of signal drivers.

    摘要翻译： 可编程逻辑集成电路器件具有增强的功能，用于在器件上动态地复用信号。 在设备上提供的用于将多个连接器输入信号中的任何一个连接到连接器输出的可控连接器由可编程选择为恒定或可变信号的控制信号控制。 如果控制信号被选择为可变信号，则由该控制信号控制的连接器可以作为到该连接器的输入信号的动态多路复用器来操作。 可控连接器可以有利地用作连接器，其用于允许几个可能的信号源有效地共享更少数量的信号驱动器。

    Coarse-grained look-up table architecture
    139.
    发明授权
    Coarse-grained look-up table architecture 有权
    粗粒查询表架构

    公开(公告)号：US06122720A

    公开(公告)日：2000-09-19

    申请号：US130874

    申请日：1998-08-07

    申请人： Richard G. Cliff

    发明人： Richard G. Cliff

    IPC分类号： H03K19/177 ,  G06F13/00

    CPC分类号： H03K19/17748 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778

    摘要： A new programmable logic device architecture with an improved LAB and improved interconnection resources. For interconnecting signals to and from the LABs (200), the global interconnection resources include switch boxes (310), long lines (340 and 350), double lines (360 and 370), single lines (385), and half- (330) and partially populated (320) multiplexer regions. The LAB includes two levels of function blocks. In a first level, there are eight four-input function blocks (601). In a second level, there are two four-input function blocks (670) and four secondary two-input function blocks (672). In one embodiment, these function blocks are implemented using look-up tables (LUTs). The LAB has combinatorial and registered outputs. The LAB also contains storage blocks (691) for implementing sequential or registered logic functions. The LAB has a carry chain for implementing logic functions requiring carry bits. The LAB may also be configured to implement a random access memory.

    摘要翻译： 一种新的可编程逻辑器件架构，具有改进的LAB和改进的互连资源。 为了将信号与LAB（200）相互连接，全局互连资源包括开关盒（310），长线（340和350），双线（360和370），单线（385）和半 - （330 ）和部分填充（320）多路复用器区域。 LAB包括两个级别的功能块。 在第一级中，有八个四输入功能块（601）。 在第二级中，存在两个四输入功能块（670）和四个辅助双输入功能块（672）。 在一个实施例中，这些功能块使用查找表（LUT）来实现。 劳顾会有组合和注册的产出。 LAB还包含用于实现顺序或注册的逻辑功能的存储块（691）。 LAB具有用于实现需要进位位的逻辑功能的进位链。 LAB还可以被配置为实现随机存取存储器。