公开(公告)号：US11422929B2

公开(公告)日：2022-08-23

申请号：US17150675

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: G06F12/02 ,  G06F12/0893 ,  G06F12/0864 ,  G06F12/06

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

公开(公告)号：US20210357691A1

公开(公告)日：2021-11-18

申请号：US16874504

申请日：2020-05-14

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo

IPC: G06K9/62 ,  G06K9/00 ,  G06K9/20 ,  G06N20/00

Abstract: Methods and apparatus for applying data analytics such as deep learning algorithms to sensor data. In one embodiment, an electronic device such as a camera apparatus including a deep learning accelerator (DLA) communicative with an image sensor is disclosed, the camera apparatus configured to evaluate unprocessed sensor data from the image sensor using the DLA. In one variant, the camera apparatus provides sensor data directly to the DLA, bypassing image signal processing in order to improve the effectiveness the DLA, obtain DLA results more quickly than using conventional methods, and further allow the camera apparatus to conserve power.

公开(公告)号：US11070257B2

公开(公告)日：2021-07-20

申请号：US16786637

申请日：2020-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04B7/0413 ,  G06N3/08 ,  G06N3/04

Abstract: Examples described herein include systems and methods, including wireless devices and systems with neuron calculators that may perform one or more functionalities of a wireless transceiver. The neuron calculator calculates output signals that may be implemented, for example, using accumulation units that sum the multiplicative processing results of ordered sets from ordered neurons with connection weights for each connection between an ordered neuron and outputs of the neuron calculator. The ordered sets may be a combination of some input signals, with the number of signals determined by an order of the neuron. Accordingly, a kth-order neuron may include an ordered set comprising product values of k input signals, where the input signals are selected from a set of k-combinations with repetition. As an example in a wireless transceiver, the neuron calculator may perform channel estimation as a channel estimation processing component of the receiver portion of a wireless transceiver.

公开(公告)号：US11032139B2

公开(公告)日：2021-06-08

申请号：US16116849

申请日：2018-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04L12/24 ,  H04L29/08 ,  H04W76/28

Abstract: Examples described herein include methods, devices, and systems which may implement different processing stages for wireless communication in processing units. Such data processing may include a source data processing stage, a baseband processing stage, a digital front-end processing stage, and a radio frequency (RF) processing stage. Data may be received from a sensor of device and then processed in the stages to generate output data for transmission. Processing the data in the various stages may occur during an active time period of a discontinuous operating mode. During the active time period, a reconfigurable hardware platform may allocate all or a portion of the processing units to implement the processing stages. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US20210143860A1

公开(公告)日：2021-05-13

申请号：US17150016

申请日：2021-01-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo

IPC: H04B1/401 ,  H04B1/44 ,  H04L25/02 ,  H04B7/08 ,  G06N3/08 ,  H04L1/00 ,  G06N3/04 ,  H04W72/04

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data delayed versions of at least a portion of the respective processing results with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data delayed versions of respective outputs of various layers of multiplication/accumulation processing units (MAC units) for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a wireless processing mode selection. In another example, such mixing input data with delayed versions of processing results may be to receive and process noisy wireless input data. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US10963265B2

公开(公告)日：2021-03-30

申请号：US15493551

申请日：2017-04-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: G06F9/38 ,  G06F15/78

Abstract: Examples described herein include systems and methods which include an apparatus comprising a plurality of configurable logic units and a plurality of switches, with each switch being coupled to at least one configurable logic unit of the plurality of configurable logic units. The apparatus further includes an instruction register configured to provide respective switch instructions of a plurality of switch instructions to each switch based on a computation to be implemented among the plurality of configurable logic units. For example, the switch instructions may include allocating the plurality of configurable logic units to perform the computation and activating an input of the switch and an output of the switch to couple at least a first configurable logic unit and a second configurable logic unit. In various embodiments, configurable logic units can include arithmetic logic units (ALUs), bit manipulation units (BMUs), and multiplier-accumulator units (MACs).

公开(公告)号：US10958593B2

公开(公告)日：2021-03-23

申请号：US16118086

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  Tamara Schmitz ,  John L. Watson ,  John Schroeter ,  Fa-Long Luo ,  Jaime Cummins

IPC: H04W4/00 ,  H04L12/933 ,  H04B7/04 ,  H04W4/80 ,  H04B5/00 ,  H04W40/06 ,  H04L12/947 ,  H04L12/931 ,  H04W84/04

Abstract: An apparatus is disclosed. The apparatus comprises a plurality of antennas and an integrated circuit chip coupled to the plurality of antennas, and is configured to process cellular signals received from the plurality of antennas in accordance with a cellular communication protocol and to process radio frequency identification (RFID) signals received from the plurality of antennas in accordance with an RFID protocol.

公开(公告)号：US20200374901A1

公开(公告)日：2020-11-26

申请号：US16989051

申请日：2020-08-10

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Glen E. Hush ,  Aaron P. Boehm

IPC: H04W72/12 ,  H04B1/38 ,  G06F9/30

Abstract: Systems, apparatuses and method related to remotely executable instructions are described. A device may be wirelessly coupled to (e.g., physically separated) another device, which may be in a physically separate device. The another device may remotely execute instructions associated with performing various operations, which would have been entirely executed at the device absent the another device. The outputs obtained as a result of the execution may be transmitted, via the transceiver, back to the device via a wireless communication link (e.g., using resources of an ultra high frequency (UHF), super high frequency (SHF), extremely high frequency (EHF), and/or tremendously high frequency (THF) bands). The another device at which the instructions are remotely executable may include memory resources, processing resources, and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).

公开(公告)号：US10716110B2

公开(公告)日：2020-07-14

申请号：US15693122

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W72/04 ,  H04W72/08 ,  H04B10/2575 ,  H04W88/08 ,  H04L29/08

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US10684955B2

公开(公告)日：2020-06-16

申请号：US15493505

申请日：2017-04-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: G06F12/10 ,  G06F12/02

Abstract: Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.