公开(公告)号：US11334134B2

公开(公告)日：2022-05-17

申请号：US17037984

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Naveen Kumar Narala ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun

IPC: G06F1/28 ,  G06F13/36

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

公开(公告)号：US11119790B2

公开(公告)日：2021-09-14

申请号：US16507947

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Lalan Jee Mishra

IPC: G06F9/445 ,  G06F1/10 ,  G06F13/42

Abstract: Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.

公开(公告)号：US11119696B2

公开(公告)日：2021-09-14

申请号：US16508136

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F3/06 ,  G06F9/30 ,  G06F13/42

Abstract: Systems, methods, and apparatus for increasing register space on a slave device are described. A method performed at a device coupled to a serial bus includes receiving a datagram from a serial bus, the datagram including a command directed to a first register address in a first page of registers, writing data in a payload of the datagram to a second register address in a second page of registers when the command is a write command, and reading data from the second register address in the second page of registers when the command is a read command. The second register address is identified in the datagram when the command is a write command.

公开(公告)号：US20210181788A1

公开(公告)日：2021-06-17

申请号：US16717838

申请日：2019-12-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F1/14 ,  G06F1/3234 ,  H04L12/40

Abstract: Single-counter, multi-trigger systems and methods in communication systems consolidate tracking of multiple trigger events into a single counter in place of plural counters. The single counter may track multiple trigger events for a single triggered element. Likewise, the single counter may track trigger events for a plurality of triggered elements. By consolidating tracking of trigger events with reference to a single counter, the size of the circuit may be reduced and power savings may be achieved.

公开(公告)号：US10592441B2

公开(公告)日：2020-03-17

申请号：US15960356

申请日：2018-04-23

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Christopher Kong Yee Chun ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad

IPC: G06F13/16 ,  G06F13/42

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

公开(公告)号：US10579581B2

公开(公告)日：2020-03-03

申请号：US16204401

申请日：2018-11-29

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

IPC: G06F13/42

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes configuring a first interface to exchange data over two primary wires of a serial bus in accordance with a first I3C protocol, and configuring a second interface to communicate over at least one secondary wire in accordance with a second I3C protocol. In one example, the first data is encoded in a sequence of symbols representing signaling state of the two primary wires. A recovered clock signal may be derived from transitions between symbol transmission intervals in the first interface may be used to control double data rate communication through the second interface.

公开(公告)号：US10545886B2

公开(公告)日：2020-01-28

申请号：US16167193

申请日：2018-10-22

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/376

Abstract: Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

公开(公告)号：US10482055B2

公开(公告)日：2019-11-19

申请号：US15974204

申请日：2018-05-08

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, apparatus, methods and techniques that can provide optimized low-latency communications between different devices such that GPIO signals may be carried as virtual signals. A virtual GPIO finite state machine in a first device is provided that can consolidate GPIO-related events by initiating a wait period after a first-occurring event and that has a duration selected to permit one or more later-occurring events to be detected before transmission of virtual GPIO data over a data communication bus to a second device. One method may include initiating a wait period after detecting a first change in GPIO state, refraining from transmitting virtual GPIO data during the wait period, detecting occurrence of a second change in GPIO state during the wait period, and transmitting virtual GPIO data corresponding to the first and second changes in GPIO state over the serial bus after the wait period has expired.

公开(公告)号：US10467154B2

公开(公告)日：2019-11-05

申请号：US15864871

申请日：2018-01-08

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun ,  Mohit Prasad ,  Chris Rosolowski

IPC: G06F13/12 ,  G06F13/364 ,  G06F13/40 ,  G06F13/42 ,  G06F15/78

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

公开(公告)号：US20190317579A1

公开(公告)日：2019-10-17

申请号：US15952071

申请日：2018-04-12

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Chiew-Guan Tan ,  Alex Kuang-Hsuan Tu

IPC: G06F1/26

Abstract: Aspects of the disclosure are directed to a System on a Chip (SOC). In accordance with one aspect, a method for implementing back power protection (BPP) in a SOC includes transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function; transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function; using the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.