公开(公告)号：US11003445B2

公开(公告)日：2021-05-11

申请号：US16163818

申请日：2018-10-18

Applicant: Shanghai Zhaoxin Semiconductor Co., Ltd.

Inventor： Jing Chen ,  Xiaoyang Li ,  Juanli Song ,  Zhenhua Huang ,  Weilin Wang ,  Jiin Lai

IPC: G06F7/38 ,  G06F9/44 ,  G06F9/22 ,  G06F9/30 ,  G06F9/448 ,  G06F7/499 ,  G06F7/533 ,  G06F15/78 ,  G06F9/38 ,  G06N3/063

Abstract: A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.

公开(公告)号：US10990414B2

公开(公告)日：2021-04-27

申请号：US15778744

申请日：2016-11-17

Applicant: NEC CORPORATION

Inventor： Yutaka Yakuwa

IPC: G06F9/44 ,  G06F9/445 ,  G06F9/48 ,  G06F8/20 ,  G06F8/35 ,  G06F9/448 ,  G06F9/38 ,  G06F9/4401

Abstract: The purpose of the present invention is to more assuredly generate a system construction procedure, while reducing the amount of calculation. This system construction assistance system is provided with: a state model dividing unit 501 that divides state models into one or more groups, on the basis of at least the dependency between state elements included in the state models; a invertibility determination unit 502 that determines the invertibility of a set of state elements belonging to a specified group; a group dependent procedure calculation unit 503 that calculates, for each group after division, a procedure for transitioning the set of state elements belonging to the group to a requested state; and a procedure integration unit 504 that integrates the procedures calculated for each group.

公开(公告)号：US10990238B2

公开(公告)日：2021-04-27

申请号：US16582244

申请日：2019-09-25

Applicant: Soroco Private Limited

Inventor： George Peter Nychis ,  Rohan Narayan Murty

IPC: G06F3/00 ,  G06F17/00 ,  G06F3/0481 ,  G06F11/36 ,  G06F3/048 ,  G06F9/451 ,  G06F16/9535 ,  G06F9/44 ,  G06F9/455 ,  G06F9/448 ,  G06F8/38 ,  G06F11/07 ,  G06F11/32 ,  G06F3/0482 ,  G06F3/0484 ,  G06F11/34

Abstract: A system comprising at least one hardware processor configured to perform: accessing a software robot computer program for controlling at least one application program to perform a task comprising a first sub-task to be performed by a first application program; generating an object hierarchy comprising a plurality of objects corresponding to active graphical user interface (GUI) elements of the first application program; and controlling the first application program to perform the first sub-task. The controlling includes identifying, using the software robot computer program, a first action to perform in furtherance of the first sub-task; automatically accessing, in the object hierarchy, a first object corresponding to a first active GUI element of the first application program, the accessing comprising refreshing the object hierarchy; and automatically using the first object to cause the first application program to at least partially perform the first action.

公开(公告)号：US20210117191A1

公开(公告)日：2021-04-22

申请号：US17133305

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Andrew Cunningham ,  Patrick Fleming ,  Naveen Lakkakula ,  Richard Guerin ,  Charitra Sankar ,  Stephen Doyle ,  Ralph Castro ,  John Browne

IPC: G06F9/30 ,  G06F9/448 ,  G06F9/48 ,  G06F11/10

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.

公开(公告)号：US20210117011A1

公开(公告)日：2021-04-22

申请号：US17116921

申请日：2020-12-09

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Carlo CRIPPA ,  Rossella BASSOLI

IPC: G06F3/01 ,  G06F9/448 ,  G06F1/16 ,  G05B19/042

Abstract: A programmable data processing circuit is configured for receiving sensor signals indicative of gestures for identification by the processing circuit. The processing circuit applies to the sensor signals finite state machine processing resources to provide identification output signals indicative of gestures identified as a function of the sensor signals. A plurality of finite state machine processing programs loaded into the processing circuit include a data section and an instruction section. The data section including a fixed size part specifying respective processing resources used by the programs in the plurality of finite state machine processing programs and a variable size part with respective sizes for allocating the respective processing resources used by the programs in the plurality of finite state machine processing programs. The instruction section including conditions and commands for execution by the respective processing resources used by the programs by operating on data located in the respective data sections.

公开(公告)号：US10977152B2

公开(公告)日：2021-04-13

申请号：US16385798

申请日：2019-04-16

Applicant: Oracle International Corporation

Inventor： Raja Chatterjee ,  James Elder Weaver

IPC: G06F11/34 ,  G06F9/448 ,  G06F11/07

Abstract: One or more embodiments analyze log records of applications to determine whether a composite rule pertaining to events associated with the log records occurring within a specified time window are satisfied. Satisfaction of the composite rule may facilitate real-time diagnosis and detection of patterns in logs which indicate problems, threats, systemic issues, or performance issues relating to the applications. The composite rule may specify events associated with log records from multiple different applications that occur within a same specified time window and are associated with a same tenant and entity. Satisfaction of the composite rule may be analyzed by a state machine that tracks satisfaction of the individual rules within the composite rule in a sequence of stages. A notification, alert, or alarm may be generated when the composite rule is satisfied.

公开(公告)号：US20210089328A1

公开(公告)日：2021-03-25

申请号：US17114382

申请日：2020-12-07

Applicant: CLOUDFLARE, INC.

Inventor： Kenton Taylor Varda ,  Zachary Aaron Bloom ,  Marek Przemyslaw Majkowski ,  Ingvar Stepanyan ,  Kyle Kloepper ,  Dane Orion Knecht ,  John Graham-Cumming ,  Dani Grant

IPC: G06F9/448 ,  H04L29/08 ,  H04L29/06 ,  G06F9/455

Abstract: A compute server receives a request from a client device that triggers execution of a third-party code piece. The compute server is one of multiple compute servers that are part of a distributed cloud computing network. The request may be an HTTP request and directed to a zone. A single process at the compute server executes the third-party code piece in an isolated execution environment. The single process is also executing other third-party code pieces in other isolated execution environments respectively. A response is generated to the request based at least in part on the executed third-party code piece, and the generated response is transmitted to the client device.

公开(公告)号：US10958256B1

公开(公告)日：2021-03-23

申请号：US17067832

申请日：2020-10-12

Applicant: Realtek Semiconductor Corp.

Inventor： Chia-Liang (Leon) Lin

IPC: H03K5/15 ,  H03K5/156 ,  G06F9/448 ,  G04F10/00 ,  H03K5/05

Abstract: A fifty percent duty cycle detector includes a single-ended-to-differential converter (S2D) configured to receive a first clock and output a second clock and a third clock that are complementary; a controllable swap circuit configured to receive the second clock and the third clock and output a fourth clock and a fifth clock in accordance with a logical control signal; a time-to-digital converter (TDC) configured to receive the fourth clock and the fifth clock and output a digital word; and a finite state machine configured to receive the digital word and output the logical control signal and a ternary decision.

公开(公告)号：US20210081306A1

公开(公告)日：2021-03-18

申请号：US16828501

申请日：2020-03-24

Applicant: Tata Consultancy Services Limited

Inventor： Supriya AGRAWAL ,  Venkatesh RAMANATHAN ,  Ulka SHROTRI ,  Amey ZARE ,  Sagar Kumar VERMA

IPC: G06F11/36 ,  G06F9/448 ,  G06F16/901

Abstract: Product testing ensures whether the product is defect free or not and it is an important part of any product before product release. Any inadequacy in testing can result in financial losses and also damage the reputation, brand, and business. Functional testing is important since it verifies that the products functioning meets its requirements. Conventional methods mainly focus on executing test cases rather than generating test cases. Hence there is challenge to create scalable test cases for products with huge volume of data and with complex features. The present disclosure generates a plurality of time bound test cases based on an Artificial Rain Drop (ARD) algorithm. Here, events associated with an event based system are compiled in a tabular format. Each of the plurality of events are represented as a regular expression. Further, timed finite automaton is constructed for each regular expression prior to applying the ARD algorithm.

公开(公告)号：US20210081297A1

公开(公告)日：2021-03-18

申请号：US17017963

申请日：2020-09-11

Applicant: ACCEMIC TECHNOLOGIES GMBH

Inventor： Alexander WEISS ,  Alexander LANGE

IPC: G06F11/34 ,  G06F11/32 ,  G06F11/273 ,  G06F9/30 ,  G06F9/448 ,  G06F9/54

Abstract: A trace-data-processing device for reconstructing an execution flow of a program performed by a source device under test or under observation, herein DUT, using at least one source-specific trace-data stream is disclosed. The trace-data-processing device comprises a trace-data-processing unit, which is configured to identify in the trace-data stream at least one instruction-synchronization message and branch messages. Moreover, the trace-data-processing device is configured to generate runtime-information data indicative of an at least partial reconstruction of the execution flow, using the identified trace messages, a pre-defined branch identifier allocated to each branch instruction address in the program that is associated with a direct branch instruction and pre-stored reconstruction information stored in a reconstruction memory.