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公开(公告)号：US20230129973A1
公开(公告)日：2023-04-27
申请号：US17939173
申请日：2022-09-07
Inventor： Reiner Welk , Danika Perrin
Abstract: In an embodiment, a radio frequency (RF) receiver circuit includes a main circuit and a wake-up circuit. The main circuit is configured to process RF signals. The wake-up circuit is configured to detect a reception of the RF signals. The wake-up circuit includes an automatic gain control (AGC) loop, and is configured to have a first operating mode where a set point voltage of the loop has a first substantially constant value, and a second operating mode where the set point voltage of the loop has a second value dependent on a power supply voltage of the wake-up circuit.
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公开(公告)号：US20230058758A1
公开(公告)日：2023-02-23
申请号：US17884245
申请日：2022-08-09
Inventor： Alexandre TRAMONI , Patrick ARNOULD
IPC: G06F1/26
Abstract: The present disclosure relates to a method for powering an electronic device. The electronic device includes at least one universal integrated circuit card or at least one secure element; at least one power supply circuit for said card or secure element; and at least one near field communication module. When the near field communication module changes from a standby or inactive state to an active state, the following successive operations are performed: —the components and circuits of said electronic device are started; —programs of the electronic device and said secure card or element are started at the same time.
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公开(公告)号：US20230055356A1
公开(公告)日：2023-02-23
申请号：US17884238
申请日：2022-08-09
Inventor： Alexandre TRAMONI , Patrick ARNOULD
IPC: G06K19/07
Abstract: The present disclosure relates to an electronic device comprising: at least one universal integrated circuit card or at least one secure element and at least one power supply circuit for said card or secure element, said power supply circuit being connected to at least a first power supply voltage source of the electronic device and comprising a voltage detector adapted to determine whether said first voltage source provides a first power supply voltage different from a reference voltage; and at least one near field communication module adapted to enter an active mode whenever said voltage detector determines that said first supply voltage is different from the reference voltage.
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公开(公告)号：US20230015669A1
公开(公告)日：2023-01-19
申请号：US17945822
申请日：2022-09-15
Inventor： David AUCHERE , Claire LAPORTE , Deborah COGONI , Laurent SCHWARTZ
Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
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公开(公告)号：US11552467B2
公开(公告)日：2023-01-10
申请号：US17157555
申请日：2021-01-25
Applicant: STMicroelectronics (Alps) SAS
Inventor： Michel Bouche
Abstract: An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.
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Patent Agency Ranking
公开(公告)号：US20220391204A1
公开(公告)日：2022-12-08
申请号：US17829784
申请日：2022-06-01
Inventor： Pierre Gobin , Jeremy Ribeiro De Freitas
Abstract: A digital signal processor according to an embodiment comprises a processing stage. The processing stage is configured to receive Cartesian coordinates of a vector in a floating point format and to output polar coordinates of the vector in a floating point format. The processing stage comprises a first electronic circuit configured to iteratively implement, timed by a clock signal, a CORDIC algorithm in a floating point format.
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公开(公告)号：US20220391171A1
公开(公告)日：2022-12-08
申请号：US17744337
申请日：2022-05-13
Inventor： Fabrice Romain , Fabien Journet
IPC: G06F7/523
Abstract: In an embodiment, after a first phase of multiplication, in an electronic multiplication circuit, of a first operand by a second operand leading to a successive delivery of least significant words of the result of the first multiplication, a second multiplication, of the first operand by a supplementary operand is implemented in the electronic multiplication circuit, during a second phase of multiplication. The supplementary operands are not all identical.
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公开(公告)号：US20220382067A1
公开(公告)日：2022-12-01
申请号：US17661381
申请日：2022-04-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Research & Development) Limited
Inventor： Quentin Mermillod-Anselme , Salim Bouchene , Adam Caley
Abstract: The present disclosure relates to an assembly for an electronic device comprising: a display screen; an optical light emitter adapted to emit an Infrared or near Infrared light beam through the display screen; the optical light emitter and the display screen being of the type that, when an unpolarized light beam from the optical light emitter passes through a region of the display screen, a white spot of a first intensity is formed in the region; a light polarizer positioned between the optical light emitter and the display screen, the light polarizer being orientated such that a white spot of a second intensity, lower than the first intensity, is formed when the light beam, from the optical light emitter and polarized by the light polarizer, passes through the region of the display screen.
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公开(公告)号：US20220376379A1
公开(公告)日：2022-11-24
申请号：US17742039
申请日：2022-05-11
Inventor： Romain COFFY , Georg KIMMICH
Abstract: A package includes an upper level mounted to a lower level. The upper level includes a stack formed by insulating layers and conductive elements and includes a first conductive track of an antenna. A plastic element rests on the stack. A first cavity is defined in the plastic element. A second conductive track of the antenna is located on a wall of the plastic element (for example, in or adjacent to the first cavity). A second cavity is also defined in the plastic element surrounding the first cavity. A third conductive track of the antenna is located on a wall of the plastic element (for example, in the second cavity). A third cavity is delimited between the upper and lower levels and an integrated circuit chip is mounted within the third cavity and electrically connected to the antenna.
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公开(公告)号：US20220374201A1
公开(公告)日：2022-11-24
申请号：US17747101
申请日：2022-05-18
Inventor： Pierre Gobin , Jeremy Ribeiro De Freitas
Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Homer methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Homer method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.
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