公开(公告)号：US20230018356A1

公开(公告)日：2023-01-19

申请号：US17812062

申请日：2022-07-12

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Hugo Gicquel ,  Sandrine Nicolas ,  Cedric Rechatin ,  Reiner Welk

IPC: H03F3/193

Abstract: In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.

公开(公告)号：US20230129973A1

公开(公告)日：2023-04-27

申请号：US17939173

申请日：2022-09-07

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Reiner Welk ,  Danika Perrin

IPC: H04W52/02 ,  H04W52/52

Abstract: In an embodiment, a radio frequency (RF) receiver circuit includes a main circuit and a wake-up circuit. The main circuit is configured to process RF signals. The wake-up circuit is configured to detect a reception of the RF signals. The wake-up circuit includes an automatic gain control (AGC) loop, and is configured to have a first operating mode where a set point voltage of the loop has a first substantially constant value, and a second operating mode where the set point voltage of the loop has a second value dependent on a power supply voltage of the wake-up circuit.

公开(公告)号：US10979063B2

公开(公告)日：2021-04-13

申请号：US16862297

申请日：2020-04-29

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Sandrine Nicolas ,  Damien Giot ,  Serge Ramet ,  Reiner Welk

IPC: H03M1/38 ,  H03M1/12 ,  H03M1/44

Abstract: An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.