公开(公告)号：US20220391171A1

公开(公告)日：2022-12-08

申请号：US17744337

申请日：2022-05-13

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice Romain ,  Fabien Journet

IPC: G06F7/523

Abstract: In an embodiment, after a first phase of multiplication, in an electronic multiplication circuit, of a first operand by a second operand leading to a successive delivery of least significant words of the result of the first multiplication, a second multiplication, of the first operand by a supplementary operand is implemented in the electronic multiplication circuit, during a second phase of multiplication. The supplementary operands are not all identical.

公开(公告)号：US11663365B2

公开(公告)日：2023-05-30

申请号：US16928901

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (ALPS) SAS

Inventor： Marc Benveniste ,  Fabien Journet ,  Fabrice Marinet

IPC: G06F21/44 ,  G06F21/72 ,  G06F21/75 ,  G06F1/08 ,  G06F3/12 ,  H04L9/32

CPC classification number: G06F21/75 ,  G06F1/08 ,  G06F3/1238 ,  G06F21/44 ,  G06F21/72 ,  H04L9/3236 ,  H04L9/3247

Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.

公开(公告)号：US10067550B2

公开(公告)日：2018-09-04

申请号：US15253012

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Fabien Journet

IPC: G06F1/32 ,  G06F9/38 ,  H04B5/00 ,  G06F1/06

Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

公开(公告)号：US11436346B2

公开(公告)日：2022-09-06

申请号：US16866088

申请日：2020-05-04

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Fabien Journet ,  Yanis Linge

IPC: G06F21/60 ,  G06F9/30 ,  G06F21/84 ,  H04L9/08

Abstract: A method and device for protecting encrypted data are disclosed. In an embodiment an integrated circuit includes a secure module including a first register containing a first mask and a second register containing masked data, the first mask and the masked data forming a secret key and a processor configured to generate a second mask and mask the secret key with the second mask when the secret key is not used for an encryption operation and during reception of a validation signal, wherein the first and second registers are disposed in the secure module so that the outputs of the registers are not simultaneously optically viewable.

公开(公告)号：US20180004270A1

公开(公告)日：2018-01-04

申请号：US15253012

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Fabien Journet

IPC: G06F1/32 ,  H04B5/00 ,  G06F1/10

CPC classification number: G06F1/324 ,  G06F1/06 ,  G06F9/3869 ,  H04B5/0037

Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.