公开(公告)号：US09281027B1

公开(公告)日：2016-03-08

申请号：US14511581

申请日：2014-10-10

Applicant: ARM LIMITED

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Mudit Bhargava

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/106 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/419 ,  G11C29/04

Abstract: A memory device includes latching circuitry for receiving a latching value and for providing said latching value as an output. A path receives said latching value and passes said latching value to said latching circuitry. First storage circuitry provides a first stored value when said memory device is in a read mode of operation. A bit line is connected to said first storage circuitry. First control circuitry selectively connects said bit line to said path. Sensing circuitry, when an enable signal is active, detects a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and outputs a latching value, dependent on said voltage change, on said path. Second storage circuitry provides a second stored value in a test mode of operation and second control circuitry receives said second stored value and selectively outputs said second stored value as said latching value on said path. Said latching circuitry outputs said latching value as said output in dependence on said enable signal, such that said enable signal controls both said latching circuitry and said sense circuitry.

Abstract translation: 存储器件包括用于接收锁存值并用于提供所述锁存值作为输出的锁存电路。 路径接收所述锁存值并将所述锁存值传递到所述锁存电路。 当所述存储器件处于读取操作模式时，第一存储电路提供第一存储值。 位线连接到所述第一存储电路。 第一控制电路选择性地将所述位线连接到所述路径。 感测电路，当使能信号有效时，由于将所述位线连接到所述第一存储电路和所述路径而检测所述路径上的电压变化，并根据所述电压变化在所述路径上输出锁存值。 第二存储电路在测试操作模式中提供第二存储值，第二控制电路接收所述第二存储值，并且有选择地将所述第二存储值输出作为所述路径上的锁存值。 所述锁存电路根据所述使能信号输出所述锁存值作为所述输出，使得所述使能信号控制所述锁存电路和所述检测电路。

公开(公告)号：US20150244371A1

公开(公告)日：2015-08-27

申请号：US14192056

申请日：2014-02-27

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018507 ,  H03K19/0013

Abstract: A level conversion circuit is provided for generating an output signal having one of a higher output level and a lower output level in response to an input signal having one of a higher input level and a lower input level. The level conversion circuit has input circuitry which, in response to a transition of the input signal between the higher and lower input levels, output a rising transition of a temporary output signal on the output line towards the higher input level. Output control circuitry detects the rising transition of the temporary output signal and pulls the output signal to the higher output level. This arrangement allows for fast level conversion without a DC leakage path.

Abstract translation: 提供电平转换电路，用于响应于具有较高输入电平和较低输入电平之一的输入信号，产生具有较高输出电平和较低输出电平之一的输出信号。 电平转换电路具有输入电路，响应于输入信号在较高和较低输入电平之间的转变，输出线路上的临时输出信号向上输入电平的上升转变。 输出控制电路检测临时输出信号的上升转换，并将输出信号拉至较高的输出电平。 这种布置允许在没有DC泄漏路径的情况下进行快速电平转换。