公开(公告)号：US20240153551A1

公开(公告)日：2024-05-09

申请号：US17980335

申请日：2022-11-03

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Vivek Asthana ,  Sony ,  Ettore Amirante ,  Yew Keong Chong

IPC分类号： G11C11/418

CPC分类号： G11C11/418

摘要： Various implementations described herein are related to a device having multi-page memory with a first core array and bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines. The device may have wordline drivers coupled to the bitcells in the first core array via the first wordlines and to the bitcells in the second core array via the second wordlines. The device may have buried metal lines formed within a substrate, and the buried metal lines may be used to couple the wordline drivers to the first wordlines.

公开(公告)号：US20240012748A1

公开(公告)日：2024-01-11

申请号：US17861084

申请日：2022-07-08

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC分类号： G06F12/02

CPC分类号： G06F12/023 ,  G06F2212/1008

摘要： According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

公开(公告)号：US11688444B2

公开(公告)日：2023-06-27

申请号：US17209876

申请日：2021-03-23

申请人： Arm Limited

发明人： Akash Bangalore Srinivasa ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sreebin Sreedhar ,  Balaji Ravikumar ,  Penaka Phani Goberu ,  Vibin Vincent

IPC分类号： G11C8/08 ,  G11C11/16 ,  G11C11/418

CPC分类号： G11C8/08 ,  G11C11/1657 ,  G11C11/418

摘要： Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.

公开(公告)号：US11676656B2

公开(公告)日：2023-06-13

申请号：US17168428

申请日：2021-02-05

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Yew Keong Chong ,  Rajiv Kumar Sisodia ,  Sriram Thyagarajan

IPC分类号： G11C11/419 ,  G11C11/412

CPC分类号： G11C11/419 ,  G11C11/412

摘要： Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

公开(公告)号：US20220319585A1

公开(公告)日：2022-10-06

申请号：US17218949

申请日：2021-03-31

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Munish Kumar ,  Ayush Kulshrestha ,  Rajiv Kumar Sisodia ,  Yew Keong Chong ,  Kumaraswamy Ramanathan ,  Edward Martin McCombs, JR.

IPC分类号： G11C11/418 ,  G11C11/16

摘要： Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.

公开(公告)号：US20220254411A1

公开(公告)日：2022-08-11

申请号：US17168428

申请日：2021-02-05

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Yew Keong Chong ,  Rajiv Kumar Sisodia ,  Sriram Thyagarajan

IPC分类号： G11C11/419 ,  G11C11/412

摘要： Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.

公开(公告)号：US11380384B2

公开(公告)日：2022-07-05

申请号：US17006689

申请日：2020-08-28

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/413

摘要： Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

公开(公告)号：US11200922B2

公开(公告)日：2021-12-14

申请号：US16725779

申请日：2019-12-23

申请人： Arm Limited

发明人： Sriram Thyagarajan ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Munish Kumar

IPC分类号： G11C7/10 ,  G11C7/22

摘要： Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.

公开(公告)号：US20210241807A1

公开(公告)日：2021-08-05

申请号：US16783104

申请日：2020-02-05

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC分类号： G11C8/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22

摘要： According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.

公开(公告)号：US10665591B2

公开(公告)日：2020-05-26

申请号：US16122752

申请日：2018-09-05

申请人： Arm Limited

发明人： Yew Keong Chong ,  Sriram Thyagarajan ,  Kumaraswamy Ramanathan ,  Damayanti Datta

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  G11C11/40 ,  H03K3/012

摘要： Briefly, embodiments of claimed subject matter relate to devices and methods for modifying, such as decreasing rise time and/or fall time, of a driver signal output. To achieve such modifications in driver output signals, additional gates may be positioned at PMOS and/or NMOS regions of a semiconductor film. In addition, at least in particular embodiments, etching of portions of one or more semiconductor regions may increase compressive or tensile stress, which may further operate to modify driver output signals.