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公开(公告)号：US20230186983A1
公开(公告)日：2023-06-15
申请号：US18167580
申请日：2023-02-10
Applicant: STMicroelectronics International N.V.
Inventor： Anuj GROVER , Tanmoy ROY , Nitin CHAWLA
IPC: G11C11/419 , H10B10/00
CPC classification number: G11C11/419 , H10B10/12
Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.
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公开(公告)号：US20230168699A1
公开(公告)日：2023-06-01
申请号：US17967498
申请日：2022-10-17
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Mayankkumar Hareshbhai Niranjani , Dhulipalla Phaneendra Kumar , Gourav Garg , Sourabh Banzal
Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
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公开(公告)号：US11665915B2
公开(公告)日：2023-05-30
申请号：US16863856
申请日：2020-04-30
Inventor： Fabio De Santis , Vikas Rana
IPC: H01L27/105 , H01L27/11521 , H01L27/112 , G11C29/00 , H01L27/11519 , H01L27/11558 , G11C16/04 , H01L21/66
CPC classification number: H01L27/1052 , G11C29/006 , H01L27/1122 , H01L27/1124 , H01L27/11519 , H01L27/11521 , H01L27/11558 , G11C16/0433 , H01L22/00
Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
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公开(公告)号：US11646741B2
公开(公告)日：2023-05-09
申请号：US17931043
申请日：2022-09-09
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Prashutosh Gupta , Ankit Gupta
CPC classification number: H03L7/0812 , H03L7/085
Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.
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公开(公告)号：US11615823B2
公开(公告)日：2023-03-28
申请号：US17542203
申请日：2021-12-03
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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Patent Agency Ranking
公开(公告)号：US20230092413A1
公开(公告)日：2023-03-23
申请号：US17800299
申请日：2021-02-15
Applicant: STMicroelectronics International N.V.
Inventor： Renaud Lemoine , Samia Ouyahia , Eric Wilhelm , Christophe Boyavalle
Abstract: According to one aspect, an integrated circuit having a radio frequency amplifier includes at least two amplifier stages and an impedance matching device between two amplifier stages of the radio frequency amplifier. The matching device includes two lines which are coupled by electromagnetic induction. The first line is connected to an output of the first amplifier stage and the second line is connected to an input of the second amplifier stage.
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公开(公告)号：US11611275B2
公开(公告)日：2023-03-21
申请号：US17866372
申请日：2022-07-15
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US20230082905A1
公开(公告)日：2023-03-16
申请号：US17800290
申请日：2021-02-15
Applicant: STMicroelectronics International N.V.
Inventor： Herve Guegnaud , Stephanie Venec , Guillaume Blamon
Abstract: According to one aspect, an integrated circuit includes a power amplifier having a succession of at least two amplifier stages. The two amplifier stages include a first amplifier stage configured to receive a radio frequency signal as input and a last amplifier stage configured to deliver as an output of an amplified radio frequency signal. The power amplifier further includes a safety circuit with a control circuit configured to compare the amplified radio frequency signal voltage with a threshold voltage. The safety circuit further comprises a gain reduction circuit configured to reduce a bias voltage of an upstream amplifier stage of the last amplifier stage when the amplified radio frequency signal voltage is greater than the threshold voltage.
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公开(公告)号：US20230061509A1
公开(公告)日：2023-03-02
申请号：US17876263
申请日：2022-07-28
Applicant: STMicroelectronics International N.V.
Inventor： Sharad GUPTA , Ankur BAL
IPC: H03M1/06
Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.
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150.发明授权公开(公告)号：US11593609B2
公开(公告)日：2023-02-28
申请号：US16794062
申请日：2020-02-18
Inventor： Giuseppe Desoli , Carmine Cappetta , Thomas Boesch , Surinder Pal Singh , Saumya Suneja
Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
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