-
公开(公告)号：US11863066B2
公开(公告)日：2024-01-02
申请号：US18168936
申请日：2023-02-14
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
-
公开(公告)号：US11798603B2
公开(公告)日：2023-10-24
申请号：US18175375
申请日：2023-02-27
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
CPC classification number: G11C7/12 , G11C7/065 , G11C7/222 , G11C11/4091 , G11C11/4094
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
-
公开(公告)号：US11665915B2
公开(公告)日：2023-05-30
申请号：US16863856
申请日：2020-04-30
Inventor： Fabio De Santis , Vikas Rana
IPC: H01L27/105 , H01L27/11521 , H01L27/112 , G11C29/00 , H01L27/11519 , H01L27/11558 , G11C16/04 , H01L21/66
CPC classification number: H01L27/1052 , G11C29/006 , H01L27/1122 , H01L27/1124 , H01L27/11519 , H01L27/11521 , H01L27/11558 , G11C16/0433 , H01L22/00
Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
-
公开(公告)号：US11615823B2
公开(公告)日：2023-03-28
申请号：US17542203
申请日：2021-12-03
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
-
公开(公告)号：US11611275B2
公开(公告)日：2023-03-21
申请号：US17866372
申请日：2022-07-15
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
-
Patent Agency Ranking
公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
Inventor： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
-
公开(公告)号：US10176869B2
公开(公告)日：2019-01-08
申请号：US16044280
申请日：2018-07-24
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
Abstract: A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.
-
公开(公告)号：US12148473B2
公开(公告)日：2024-11-19
申请号：US17697846
申请日：2022-03-17
Inventor： Roberto Bregoli , Vikas Rana
Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.
-
公开(公告)号：US20220319598A1
公开(公告)日：2022-10-06
申请号：US17697846
申请日：2022-03-17
Inventor： Roberto Bregoli , Vikas Rana
IPC: G11C16/04 , H01L27/11524 , H01L27/1156 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.
-
公开(公告)号：US11205462B2
公开(公告)日：2021-12-21
申请号：US17010704
申请日：2020-09-02
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/10 , G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.021 seconds)
