公开(公告)号：US3760354A

公开(公告)日：1973-09-18

申请号：US3760354D

申请日：1971-07-23

Applicant: DATA CONTROL SYSTEMS INC

Inventor： GINN D

IPC: H04L1/24 ,  H04L7/04 ,  G08C25/00 ,  H04L7/08

CPC classification number: H04L1/242 ,  H04L1/241 ,  H04L7/043

Abstract: A system for determining the error rate of a data communications link in which a locally generated code is synchronized to a pseudo-random code transmitted over the link and compared therewith to ascertain errors.

Abstract translation: 一种用于确定数据通信链路的错误率的系统，其中本地生成的代码与通过链路发送的伪随机码同步，并与之进行比较以确定错误。

公开(公告)号：US3596245A

公开(公告)日：1971-07-27

申请号：US3596245D

申请日：1969-05-21

Applicant: HEWLETT PACKARD LTD

Inventor： FINNIE BRIAN ,  HODGE STEPHEN R

IPC: H04J3/14 ,  H04L1/24 ,  H04L25/04 ,  H04B3/46 ,  G08C25/00 ,  H03K5/18

CPC classification number: H04L1/242 ,  H04J3/14 ,  H04L1/241

Abstract: A controllable shift register is used in testing circuitry which measures statistical error rates and synchronization loss rates on digital data links such as are used for transmission of pulsecode modulated (PCM) signals by injecting into the data link a digital test signal having accurately known statistics and then comparing the resultant received signal with a test signal generated at the receiver for providing the desired error information.