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151.发明申请公开(公告)号：US20170324426A1
公开(公告)日：2017-11-09
申请号：US15644455
申请日：2017-07-07
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1177 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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152.发明申请公开(公告)号：US20170238315A1
公开(公告)日：2017-08-17
申请号：US15504298
申请日：2015-08-25
Inventor： Jae-Young LEE , Sung-Ik PARK , Sun-Hyoung KWON , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H04W72/0446 , H04J11/004 , H04L1/0063 , H04L1/0071 , H04L5/22 , H04L27/26 , H04L27/2602 , H04L27/34 , H04L65/4076 , H04W52/04 , H04W52/346 , Y02D70/00
Abstract: An apparatus and method for broadcast signal frame using layered division multiplexing are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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153.发明申请公开(公告)号：US20170195742A1
公开(公告)日：2017-07-06
申请号：US15188943
申请日：2016-06-21
Inventor： Hye-Ju OH , Byung-Jun BAE , Hyun-Jeong YIM , Soon-Choul KIM , Hyoung-Soo LIM , Nam-Ho HUR
IPC: H04N21/6405 , H04N21/236
CPC classification number: H04N21/6405 , H04N21/236 , H04N21/4825 , H04N21/64322 , H04N21/8456 , H04N21/85406
Abstract: Disclosed herein is an apparatus and method for providing a broadcast service. The apparatus for providing a broadcast service includes a segment and metadata creation unit for creating a media segment file and profile information for a broadcast streaming service, a transfer processing unit for performing packetization and configuring a transport session in order to transfer audio/video and data objects, which correspond to the media segment file, and a broadcast transmission unit for formatting a media stream, received from the transfer processing unit, according to a broadcast signal format by multiplexing the media stream based on a layer, for creating a broadcast transmission frame that includes signaling information, and for transmitting the broadcast transmission frame via a broadcast network.
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公开(公告)号：US20170149449A1
公开(公告)日：2017-05-25
申请号：US15426940
申请日：2017-02-07
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/1105 , H03M13/17 , H03M13/2792 , H03M13/6522 , H04L1/0041 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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公开(公告)号：US20170149448A1
公开(公告)日：2017-05-25
申请号：US15426927
申请日：2017-02-07
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/17 , H03M13/255 , H03M13/27 , H03M13/2778 , H03M13/2792 , H03M13/618 , H03M13/6522
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
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Patent Agency Ranking
公开(公告)号：US20170117920A1
公开(公告)日：2017-04-27
申请号：US15401819
申请日：2017-01-09
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/1128 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
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公开(公告)号：US20170093431A1
公开(公告)日：2017-03-30
申请号：US15372707
申请日：2016-12-08
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2757 , H03M13/1165 , H03M13/255 , H03M13/2778 , H03M13/2792 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L1/0076 , H04L2001/0093
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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158.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 审中-公开低密度奇偶校验编码器的长度为64800，编码速率为3/15，低密度奇偶校验编码方法使用该方法公开(公告)号：US20170054451A1
公开(公告)日：2017-02-23
申请号：US15346004
申请日：2016-11-08
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/1102 , H03M13/116 , H03M13/1185 , H04L1/0041 , H04L1/0057 , H04L1/0058
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800，码率为3/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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159.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 审中-公开低密度奇偶校验编码器具有16200的长度和5/15的编码速率，以及使用该密码的低密度奇偶校验编码方法公开(公告)号：US20170012648A1
公开(公告)日：2017-01-12
申请号：US15272163
申请日：2016-09-21
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/255 , H03M13/036 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/616 , H04L1/0043 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为16200且码率为5/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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160.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 审中-公开用于低密度奇偶校验的位交换机检查长度为64800的长度和2/15和4096符号映射的代码率，以及使用相同的位交互方法公开(公告)号：US20160241266A1
公开(公告)日：2016-08-18
申请号：US14671482
申请日：2015-03-27
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储具有长度为64800和码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于4096符号映射的调制器。
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