公开(公告)号：US20230066955A1

公开(公告)日：2023-03-02

申请号：US18049522

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj Sastry

IPC: H04L9/08 ,  H04L9/06

Abstract: A method comprises receiving an image of an update for a software module, a rate parameter, an index parameter, and a public key, generating a 32-byte aligned string, computing a state parameter using the 32-byte aligned string, generating a modified message representative, computing a Merkle Tree root node, and in response to a determination that the Merkle Tree root node matches the public key, forwarding, to a remote device, the image of the update for a software module, the state parameter; and the modified message representative.

公开(公告)号：US20220255757A1

公开(公告)日：2022-08-11

申请号：US17732852

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry ,  Prakash Iyer ,  Ting Lu

IPC: H04L9/32 ,  H04L9/30 ,  H04L9/06 ,  G06F7/72

Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.

公开(公告)号：US20220247561A1

公开(公告)日：2022-08-04

申请号：US17699830

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Manoj Sastry

IPC: H04L9/30

Abstract: A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.

公开(公告)号：US20220224501A1

公开(公告)日：2022-07-14

申请号：US17706939

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Manoj Sastry ,  Christopher Hall ,  Marcio Juliato ,  Shabbir Ahmed ,  Qian Wang

IPC: H04L7/00

Abstract: Time recovery techniques are described. A method comprises receiving messages from the first device by the second device in the first network domain, the messages to comprise time information to synchronize a first clock for the first device and a second clock for the second device to a network time, determining the second clock is to recover the network time for the second device without new messages from the first device, retrieving a first set of timestamps previously stored for events in the first network domain using the network time from the second clock, retrieving a second set of timestamps previously stored for the events in the first network domain using a redundant time from a third clock, where the third clock is not synchronized with the first and second clocks, and recovering the network time using a regression model and the redundant time from the third clock.

公开(公告)号：US11386204B2

公开(公告)日：2022-07-12

申请号：US17031140

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Manoj Sastry ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Qian Wang ,  Vuk Lesi

IPC: G06F21/55 ,  G06F21/85 ,  G06F21/71

Abstract: A platform comprising numerous reconfigurable circuit components arranged to operate as primary and redundant circuits is provided. The platform further comprises security circuitry arranged to monitor the primary circuit for anomalies and reconfigurable circuit arranged to disconnect the primary circuit from a bus responsive to detection of an anomaly. Furthermore, the present disclosure provides for the quarantine, refurbishment and designation as redundant, the anomalous circuit.

公开(公告)号：US11356251B2

公开(公告)日：2022-06-07

申请号：US16720671

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Dave Cavalcanti ,  Manoj Sastry

IPC: H04L29/06 ,  H04L9/08 ,  H04L9/32 ,  H04L9/40

Abstract: Systems, apparatus, methods, and techniques for facilitating privacy preserving secure communicating in a platoon of devices, such as, vehicles, roadside units, or the like is provided. A service initiator provisions a ring key-set as well as a public key-pair and distributes the keys to user equipment and service coordinators. During operation, user equipment can query, via a service coordinator, the existence of a platoon, form a platoon, or join a platoon with the ring key-set and the public key-pair. To form a platoon the service coordinator can generate a symmetric key and provide the symmetric key to the user equipment. Subsequently, user equipment can communicate using the symmetric key.

公开(公告)号：US20220166771A1

公开(公告)日：2022-05-26

申请号：US17650767

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Xiruo Liu ,  Rafael Misoczki ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/08

Abstract: In one example a prover device comprises one or more processors, a computer-readable memory, and signature logic to store a first cryptographic representation of a first trust relationship between the prover device and a verifier device, the first cryptographic representation based on a pair of asymmetric hash-based multi-time signature keys, receive an attestation request message from the verifier device, the attestation request message comprising attestation data for the verifier device and a hash-based signature generated by the verifier device, and in response to the attestation request message, to verify the attestation data, verify the hash-based signature generated by the verifier device using a public key associated with the verifier device, generate an attestation reply message using a hash-based multi-time private signature key and send the attestation reply message to the verifier device. Other examples may be described.

公开(公告)号：US11323268B2

公开(公告)日：2022-05-03

申请号：US16456368

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry ,  Prakash Iyer ,  Ting Lu

IPC: H04L9/32 ,  H04L9/30 ,  H04L9/06 ,  G06F7/72

Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.

公开(公告)号：US20220123943A1

公开(公告)日：2022-04-21

申请号：US17562461

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

公开(公告)号：US20220094517A1

公开(公告)日：2022-03-24

申请号：US17025337

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  G06F7/72 ,  H04L9/06 ,  G06N3/08

Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus.