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公开(公告)号：US12047514B2
公开(公告)日：2024-07-23
申请号：US17732852
申请日：2022-04-29
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
CPC classification number: H04L9/3247 , G06F7/725 , H04L9/0643 , H04L9/3066 , H04L9/3234 , H04L9/3236 , H04L9/3252
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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公开(公告)号：US20230114206A1
公开(公告)日：2023-04-13
申请号：US17990309
申请日：2022-11-18
Applicant: Intel Corporation
Inventor： Ke Han , Mingqiu Sun , Dong Wang , Prakash Iyer , Stephan Jourdan , Andrzej Mialkowski
IPC: G06F1/329 , G06F1/3296 , G06F9/48
Abstract: Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.
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公开(公告)号：US20220255757A1
公开(公告)日：2022-08-11
申请号：US17732852
申请日：2022-04-29
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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公开(公告)号：US11323268B2
公开(公告)日：2022-05-03
申请号：US16456368
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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Patent Agency Ranking
公开(公告)号：US20190319805A1
公开(公告)日：2019-10-17
申请号：US16456368
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Manoj Sastry , Prakash Iyer , Ting Lu
Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
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6.发明申请公开(公告)号：US20200167506A1
公开(公告)日：2020-05-28
申请号：US16586131
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Prakash Iyer , Eric Innis , Evan Custodio , Ting Lu
IPC: G06F21/76
Abstract: A PCIe card includes an FPGA and a memory that is discrete from the FPGA. The memory is accessible by the FPGA and not other devices on the card. The FPGA's core fabric is configured with a security processor that verifies a bitstream loaded through the FGPA into the memory as authentic or not authentic to limit unauthorized access to data from a user circuit that is associated with a not authentic bitstream. The security processor is loaded into the FPGA when a request is made for bitstream verification and is allowed to be overwritten after the security processor processes the bitstream to determine if the bitstream is authentication or not authentic. Allowing the security processor to be overwritten allows for high percentage usage of the core fabric for user circuits and limits the inclusion of a static circuit in the core fabric that is infrequently used.
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公开(公告)号：US20240106644A1
公开(公告)日：2024-03-28
申请号：US17954157
申请日：2022-09-27
Applicant: Intel Corporation
Inventor： Aditya Katragada , Geoffrey Strongin , Prakash Iyer , Rajesh Banginwar , Poh Thiam Teoh , Gary Wallichs
IPC: H04L9/08
CPC classification number: H04L9/0891 , H04L9/0894
Abstract: A system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint HW based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.
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公开(公告)号：US11526205B2
公开(公告)日：2022-12-13
申请号：US15734820
申请日：2018-12-31
Applicant: Intel Corporation
Inventor： Ke Han , Mingqiu Sun , Dong Wang , Prakash Iyer , Stephan Jourdan , Andrzej Mialkowski
IPC: G06F1/32 , G06F9/48 , G06F1/329 , G06F1/3296
Abstract: Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.
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公开(公告)号：US20210232199A1
公开(公告)日：2021-07-29
申请号：US15734820
申请日：2018-12-31
Applicant: Intel Corporation
Inventor： Ke Han , Mingqiu Sun , Dong Wang , Prakash Iyer , Stephan Jourdan , Andrzej Mialkowski
IPC: G06F1/329 , G06F1/3296 , G06F9/48
Abstract: Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.
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