公开(公告)号：US11574877B2

公开(公告)日：2023-02-07

申请号：US17088606

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/16 ,  H01L21/48 ,  H01L23/498

Abstract: According to various examples, a device is described. The device may include a stiffener member including a first step section and a second step section. The device may also include a plurality of vias extending from or through the stiffener member. The device may be coupled to a printed circuit board.

公开(公告)号：US11562963B2

公开(公告)日：2023-01-24

申请号：US16987440

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Sameer Shekhar ,  Amit Jain

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

公开(公告)号：US11557552B2

公开(公告)日：2023-01-17

申请号：US16818603

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Jackson Chung Peng Kong ,  Bok Eng Cheah

IPC: H01L23/66 ,  H01L23/498

Abstract: A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.

公开(公告)号：US11545434B2

公开(公告)日：2023-01-03

申请号：US16987405

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Yang Liang Poh ,  Kooi Chi Ooi

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

Abstract: The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

公开(公告)号：US11476198B2

公开(公告)日：2022-10-18

申请号：US17024182

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kok Keng Wan

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/50 ,  H01L21/60

Abstract: Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.

公开(公告)号：US11462468B2

公开(公告)日：2022-10-04

申请号：US16987409

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/50 ,  H01L23/367 ,  H01R12/75 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor package may include a semiconductor device coupled to a package substrate. The semiconductor package may also include an integrated heat spreader coupled to the package substrate. The semiconductor package may further include a package connector mounted on the integrated heat spreader. According to various examples, a semiconductor system is also described. The semiconductor system may include a first semiconductor package. The first semiconductor package may include a first package connector, and a first integrated heat spreader. The first package connector may be mounted on the first integrated heat spreader. The semiconductor system may also include a second semiconductor package. The second semiconductor package may include a second package connector, and a second integrated heat spreader. The second package connector may be mounted on the second integrated heat spreader. The first package connector may be electrically connected to the second package connector.

公开(公告)号：US20220302033A1

公开(公告)日：2022-09-22

申请号：US17631254

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

Abstract: Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.

公开(公告)号：US20220278084A1

公开(公告)日：2022-09-01

申请号：US17638039

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L25/00

Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

公开(公告)号：US11342289B2

公开(公告)日：2022-05-24

申请号：US17087667

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim ,  Kooi Chi Ooi

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01G4/224 ,  H01L23/00 ,  H01L25/18

Abstract: The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module.

公开(公告)号：US11227841B2

公开(公告)日：2022-01-18

申请号：US16419683

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H01L23/00 ,  H01L23/522

Abstract: To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip.