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    Embedded bridge substrate having an integral device
    1.
    发明授权
    Embedded bridge substrate having an integral device 有权

    公开(公告)号：US11133256B2

    公开(公告)日：2021-09-28

    申请号：US16446920

    申请日：2019-06-20

    Applicant: Intel Corporation

    Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

    IPC: H01L23/538 ,  H01L49/02 ,  H01L23/00

    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

    TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS
    6.
    发明公开
    TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS 审中-公开

    公开(公告)号：US20230317773A1

    公开(公告)日：2023-10-05

    申请号：US17711736

    申请日：2022-04-01

    Applicant: Intel Corporation

    Inventor： Sameer Shekhar ,  Amit K. Jain ,  Chin Lee Kuan

    IPC: H01L49/02 ,  H03H1/00

    CPC classification number: H01L28/92 ,  H03H1/0007 ,  H03H2001/0014

    Abstract: Technologies for low-leakage and low series resistance on-chip capacitors are disclosed. In the illustrative embodiment, each electrode of a capacitor is formed from two metal layers and vias between the metal layers. A high-k dielectric layer is between the metal layers. The electrodes are displaced relative to each other on the plane defined by the high-k dielectric layer. As a result, electric field lines of the capacitor are parallel to the high-k dielectric layer. The electrodes can be displaced from each other by more than the thickness of the high-k dielectric layer, reducing the leakage current through the high-k dielectric layer as compared to a capacitor with field lines perpendicular to the high-k dielectric layer. Such a capacitor may be used to provide power to circuits in a low-power state with little leakage current and/or may be used to absorb radiofrequency (RF) interference.

    Magnetic sensing scheme for voltage regulator circuit
    7.
    发明授权
    Magnetic sensing scheme for voltage regulator circuit 有权

    公开(公告)号：US11502603B2

    公开(公告)日：2022-11-15

    申请号：US16452322

    申请日：2019-06-25

    Applicant: Intel Corporation

    Inventor： Amit Kumar Jain ,  Chin Lee Kuan ,  Sameer Shekhar

    IPC: H02M3/158 ,  H01F27/28 ,  G01R19/165 ,  G06F1/26 ,  H01F27/40 ,  G01R33/028 ,  H02M3/156 ,  H02M1/00

    Abstract: Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.

    PACKAGE EDGE MOUNTED FRAME STRUCTURES
    8.
    发明申请
    PACKAGE EDGE MOUNTED FRAME STRUCTURES 审中-公开

    公开(公告)号：US20200098674A1

    公开(公告)日：2020-03-26

    申请号：US16142249

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Chin Lee Kuan ,  Amit Kumar Jain ,  Sameer Shekhar

    IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

    Abstract: Embodiments may relate to a semiconductor package. A conductive frame may be coupled with the semiconductor package. The conductive frame may include a first portion, a second portion, and a third portion positioned between the first portion and the second portion. The first portion may be coupled with the first side of the semiconductor package. The second portion may be coupled with the second side of the semiconductor package. The third portion may be coupled with the sidewall of the semiconductor package. Other embodiments may be described or claimed.

    APPARATUSES, METHODS, AND SYSTEMS WITH CROSS-COUPLING NOISE REDUCTION
    10.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS WITH CROSS-COUPLING NOISE REDUCTION 有权
    具有交叉耦合噪声减少的装置，方法和系统

    公开(公告)号：US20160181812A1

    公开(公告)日：2016-06-23

    申请号：US14575900

    申请日：2014-12-18

    Applicant: Intel Corporation

    Inventor： Amit K. Jain ,  Sameer Shekhar

    IPC: H02J4/00 ,  H03H7/48

    CPC classification number: H02J4/00 ,  H01F5/00 ,  H03H1/0007 ,  H03H7/00 ,  H03H7/09 ,  H03H7/1725 ,  H03H7/48 ,  H03H2001/0078

    Abstract: Embodiments include apparatuses, methods, and systems with cross-coupling noise reduction in circuits. In embodiments, a circuit may include a common inductor and a negatively coupled inductor pair connected or coupled between the first inductor and a first load and a second load. The negatively coupled inductor pair may include a first and a second inductor. The first inductor may be connected or coupled to the first load and the second inductor may be connected or coupled to the second load to reduce cross-coupling noise between the first load and the second load. Examples of passive structures that may be used to implement the circuit are also described. Other embodiments may also be described and claimed.

    Abstract translation: 实施例包括在电路中具有交叉耦合噪声降低的装置，方法和系统。 在实施例中，电路可以包括在第一电感器和第一负载和第二负载之间连接或耦合的公共电感器和负耦合电感器对。 负耦合电感器对可以包括第一和第二电感器。 第一电感器可以连接或耦合到第一负载，并且第二电感器可以连接或耦合到第二负载，以减少第一负载和第二负载之间的交叉耦合噪声。 还描述了可用于实现电路的无源结构的示例。 也可以描述和要求保护其他实施例。

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