公开(公告)号：US07213101B1

公开(公告)日：2007-05-01

申请号：US11043750

申请日：2005-01-25

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G06F12/00

CPC classification number: H04L45/00 ,  G11C15/00 ,  H04L45/7453

Abstract: A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) Address processing. A binary CAM array is segmented into a plurality of array groups, each of which includes a number of rows of binary CAM cells, a group global mask circuit, and a mask valid bit indicating whether the group global mask circuit stores a valid group global mask.

Abstract translation: 一种使用二进制CAM阵列实现无类别域间路由（CIDR）地址处理的方法和装置。 二进制CAM阵列被分割成多个阵列组，每个阵列组包括多行二进制CAM单元，组全局掩模电路和掩码有效位，指示组全局掩码电路是否存储有效的组全局掩码 。

公开(公告)号：US07193877B1

公开(公告)日：2007-03-20

申请号：US11256066

申请日：2005-10-21

Applicant: Sadashiva R. Yelluru

Inventor： Sadashiva R. Yelluru

IPC: G11C15/04 ,  G11C29/00

CPC classification number: G11C29/28 ,  G11C15/00 ,  G11C2029/2602

Abstract: A CAM device having internal circuitry to reduce test time through parallel test setup and parallel pass/fail result generation. A plurality of match results is generated in parallel within a plurality of CAM blocks of the CAM device in response to a search instruction, each match result including a block flag signal that indicates whether a match was detected within a corresponding one of the CAM blocks and a block index that indicates a location of an entry within the one of the CAM blocks. The block index and block flag signal of a highest priority one of the match results is output from the CAM device if an operating mode value indicates a first operating mode, and the block flag signals of the plurality of match results is output from the CAM device if the operating mode value indicates a test operating mode.

Abstract translation: 具有内部电路的CAM设备，通过并行测试设置和并行通过/失败结果生成来减少测试时间。 响应于搜索指令，在CAM设备的多个CAM块内并行地生成多个匹配结果，每个匹配结果包括指示在相应的一个CAM块内是否检测到匹配的块标志信号，以及 指示在一个CAM块内的条目的位置的块索引。 如果操作模式值指示第一操作模式，则从CAM设备输出匹配结果中最高优先级的块的块索引和块标志信号，并且从CAM设备输出多个匹配结果的块标志信号 如果操作模式值指示测试操作模式。

公开(公告)号：US07173837B1

公开(公告)日：2007-02-06

申请号：US10931960

申请日：2004-08-31

Applicant: Roger Bettman ,  Eric H. Voelkel

Inventor： Roger Bettman ,  Eric H. Voelkel

IPC: G11C15/00 ,  G11C11/00 ,  G11C8/00 ,  G06F13/00

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

公开(公告)号：US07149101B1

公开(公告)日：2006-12-12

申请号：US11014123

申请日：2004-12-15

Applicant: Hari Om ,  Andrew Wright

Inventor： Hari Om ,  Andrew Wright

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) device (200) can include a control block (202) having a dummy control circuit (216). A dummy control circuit (216) can initiate dummy searches (or other operations) prior to and/or during actual searches to reduce overall supply current transients. Methods for initiating dummy searches are also disclosed.

Abstract translation: 内容可寻址存储器（CAM）设备（200）可以包括具有虚拟控制电路（216）的控制块（202）。 虚拟控制电路（216）可以在实际搜索之前和/或期间启动虚拟搜索（或其他操作）以减少总体电源电流瞬变。 还公开了用于启动虚拟搜索的方法。

公开(公告)号：US07133302B1

公开(公告)日：2006-11-07

申请号：US10713185

申请日：2003-11-15

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna ,  Bindiganavale S. Nataraj

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna ,  Bindiganavale S. Nataraj

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.

Abstract translation: 低功率内容可寻址存储器（CAM）设备。 CAM设备接收N位比较值，并且作为响应，在CAM设备内激活小于N个比较线，以将比较值的N个比特中的每一个与耦合到N个比较线的CAM小区的内容进行比较。

公开(公告)号：US07126837B1

公开(公告)日：2006-10-24

申请号：US11090116

申请日：2005-03-24

Applicant: Bartosz Banachowicz ,  Andrew Wright

Inventor： Bartosz Banachowicz ,  Andrew Wright

IPC: G11C5/06

CPC classification number: G11C5/025 ,  G11C15/00 ,  G11C15/02 ,  G11C15/04 ,  G11C15/046 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/1776 ,  H03K19/1778

Abstract: A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.

Abstract translation: 存储器/逻辑单元布局结构包括形成在衬底上的一对存储器/逻辑单元。 每个存储器/逻辑单元（102,104）可以包括一对存储数据（106-0 / 106-1,106-2/106-3）的存储器区域和逻辑部分（108-0,08-1 ），其接收存储在其中的数据。 存储区域和每个存储器/逻辑单元的逻辑部分可以以L，U，S，T或Z的形状布置在衬底上，以形成一对互锁存储器/逻辑单元。

公开(公告)号：US07113415B1

公开(公告)日：2006-09-26

申请号：US10859477

申请日：2004-06-01

Applicant: Sandeep Khanna

Inventor： Sandeep Khanna

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corresponding match line segment, and a match line control circuit having an input coupled to the corresponding match line segment, an output coupled to the match line segment in a next row segment, and a control terminal to receive a corresponding enable signal. The configuration circuit has an input to receive configuration information indicative of a width and depth configuration of the CAM array and having outputs to generate the enable signals.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列和配置电路。 CAM阵列具有多行CAM单元，每行分割成多个行段，每行段包括耦合到对应匹配线段的多个CAM单元，以及匹配线控制电路，其输入耦合到 相应的匹配线段，耦合到下一行段中的匹配线段的输出，以及用于接收相应使能信号的控制终端。 配置电路具有用于接收指示CAM阵列的宽度和深度配置并具有输出以产生使能信号的配置信息的输入。

公开(公告)号：US07002823B1

公开(公告)日：2006-02-21

申请号：US10752889

申请日：2004-01-07

Applicant: Michael E. Ichiriu

Inventor： Michael E. Ichiriu

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G06F11/1064

Abstract: A content addressable memory (CAM) device having a simultaneous write and compare function. The CAM device includes a plurality of rows of CAM cells, and match lines and word lines coupled to the rows of CAM cells. The CAM device further includes a plurality of switching circuits coupled to the word lines and the match lines, each switching circuit being adapted to selectively disable assertion of a match signal on a corresponding one of the match lines based, at least in part, on the state of a corresponding one of the word lines.

Abstract translation: 一种具有同时写入和比较功能的内容可寻址存储器（CAM）装置。 CAM设备包括多行CAM单元，并且匹配耦合到CAM单元行的行和字线。 CAM设备还包括耦合到字线和匹配线的多个开关电路，每个开关电路适于至少部分地基于所述匹配线选择性地禁用对应的匹配线上的匹配信号的断言 相应的一行字线的状态。

公开(公告)号：US06961810B2

公开(公告)日：2005-11-01

申请号：US10743962

申请日：2003-12-22

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00 ,  G11C15/04 ,  G06F12/02

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract translation: CAM器件在一个时钟周期内执行：（1）从比较总线接收比较数据; （2）收到指示; （3）比较数据与第一组CAM单元进行比较; （4）生成CAM阵列中存储与比较数据匹配的数据的位置的匹配地址; （5）访问存储在CAM阵列中的CAM单元的第二组中的数据，其中第二组CAM单元可以存储与匹配位置相关联的数据; 和（6）输出到输出总线匹配地址，存储在第二组CAM单元中的数据和/或对应于匹配地址或第二组CAM单元的状态信息。

公开(公告)号：US06944709B2

公开(公告)日：2005-09-13

申请号：US09999798

申请日：2001-10-31

Applicant: Bindiganavale S. Nataraj ,  Nilesh A. Gharia ,  Rupesh R. Roy ,  Jose P. Pereira ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Hok F. Wong

Inventor： Bindiganavale S. Nataraj ,  Nilesh A. Gharia ,  Rupesh R. Roy ,  Jose P. Pereira ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Hok F. Wong

IPC: G11C15/00 ,  G11C15/04 ,  H03K3/356 ,  H03K23/56 ,  G06F13/00

CPC classification number: H03K3/356139 ,  G11C15/00 ,  G11C15/04 ,  H03K23/56

Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.

Abstract translation: 一种内容可寻址存储器（CAM）装置，包括多个CAM块和块控制电路。 多个CAM块各自包括用于存储数据字的CAM单元的阵列和优先级数存储电路的阵列以存储优先权号。 每个优先权数字指示相对于数据字中的其他数据字的相应一个数据字的优先级。 块控制电路具有用于接收类码的输入和用于向多个CAM块输出多个选择信号的电路。 每个选择信号选择性地禁用多个CAM块中的相应一个参与根据类代码的比较操作。