Flexible 2T-based fuzzy and certain matching arrays
    161.
    发明授权
    Flexible 2T-based fuzzy and certain matching arrays 有权
    灵活的基于2T的模糊和某些匹配阵列

    公开(公告)号:US08917551B2

    公开(公告)日:2014-12-23

    申请号:US13347913

    申请日:2012-01-11

    CPC classification number: G11C16/0483 G11C16/0441 G11C16/10

    Abstract: A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both program and erase operation, while 2T ROM cell preferably to use phosphorus for ROM code implant to get negative Vt0.

    Abstract translation: 公开了一种用于PLD,PAL和匹配功能的NAND阵列的基于NVM的2T或2nT NAND单元。 优选的NVM单元可以是ROM或Flash。 2T闪存单元优选地使用FN进行编程和擦除操作,而2T ROM单元优选地将磷用于ROM代码注入来获得负Vt0。

    Method and device for automatically calibrating touch detection
    163.
    发明授权
    Method and device for automatically calibrating touch detection 有权
    用于自动校准触摸检测的方法和装置

    公开(公告)号:US08884631B2

    公开(公告)日:2014-11-11

    申请号:US13113537

    申请日:2011-05-23

    CPC classification number: G06F3/0418

    Abstract: A method and device for automatically calibrating touch detection is disclosed. The present invention includes providing a sensing layer including a plurality of sensors, and each sensor senses a sensing range, and the sensing ranges of the sensors intersecting each other to form a crossing array; continuously detecting signals of the sensors as a detection signal set; performing update of an initial signal set based on the detection signal set; and when a default signal set does not match the initial signal set and the default signal set matches the detection signal set, performing update of the initial signal set.

    Abstract translation: 公开了一种用于自动校准触摸检测的方法和装置。 本发明包括提供包括多个传感器的感测层,并且每个传感器感测感测范围,并且传感器的感测范围彼此相交以形成交叉阵列; 连续检测传感器的信号作为检测信号组; 基于检测信号组执行初始信号集的更新; 并且当默认信号组与初始信号组不匹配并且默认信号组与检测信号组匹配时,执行初始信号组的更新。

    Systems and methods for image archaeology
    164.
    发明授权
    Systems and methods for image archaeology 有权
    图像考古系统和方法

    公开(公告)号:US08849058B2

    公开(公告)日:2014-09-30

    申请号:US12861377

    申请日:2010-08-23

    CPC classification number: G06T7/0022 G06T7/254 G06T7/97 G06T11/60

    Abstract: Systems and methods are described for determining manipulation history among a plurality of images. The described techniques include selecting a pair of images from the plurality of images, detecting one or more manipulations operable to transform one of the images to the other, and based on the manipulations detected, determining a parent-child relationship between the pair or pairs of images. The described techniques can further include repeating the selecting two images, detecting manipulations, and determining the parent-child relationship for each pairs of images in the plurality of images, constructing a visual migration map for the images, and presenting the visual migration map in a user readable format.

    Abstract translation: 描述了用于确定多个图像之间的操作历史的系统和方法。 所描述的技术包括从多个图像中选择一对图像,检测可操作以将图像中的一个图像转换为另一图像的一个或多个操作,并且基于检测到的操作,确定一对或多对图像之间的父子关系 图片。 所描述的技术可以进一步包括重复选择两个图像,检测操作,以及确定多个图像中每对图像的父子关系,构建图像的视觉迁移图,以及将视觉迁移图呈现在 用户可读格式。

    EEPROM-based, data-oriented combo NVM design
    166.
    发明授权
    EEPROM-based, data-oriented combo NVM design 有权
    基于EEPROM的数据导向组合NVM设计

    公开(公告)号:US08809148B2

    公开(公告)日:2014-08-19

    申请号:US13200142

    申请日:2011-09-19

    Abstract: A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

    Abstract translation: 非易失性存储器件具有FLOTOX EEPROM非易失性存储器阵列的组合。 每个基于FLOTOX的非易失性存储器阵列由基于FLOTOX的非易失性存储器单元形成,其包括至少一个浮置栅极隧穿氧化物晶体管,使得控制栅极与浮置栅极隧道氧化物晶体管的浮置栅极的耦合比率约为60 %至约70%,并且将浮置栅极与漏极区域的浮动栅极氧化物晶体管的耦合比保持为约10%至约20%的常数,并且使得沟道区的沟道长度为 减小,使得在编程过程期间将负编程电压电平施加到控制栅极,并且向漏极区域施加中等的正编程电压电平,以防止中等正编程电压电平超过漏源至源极击穿电压。

    SYSTEMS AND METHODS FOR AUTOMATICALLY DETERMINING AN IMPROVED VIEW FOR A VISUAL QUERY IN A MOBILE SEARCH
    167.
    发明申请
    SYSTEMS AND METHODS FOR AUTOMATICALLY DETERMINING AN IMPROVED VIEW FOR A VISUAL QUERY IN A MOBILE SEARCH 审中-公开
    用于自动确定移动浏览视觉查询的改进视图的系统和方法

    公开(公告)号:US20140222783A1

    公开(公告)日:2014-08-07

    申请号:US13983265

    申请日:2012-04-16

    CPC classification number: G06F16/532 G06F16/583 G06K9/00671

    Abstract: Systems and methods for automatically determining an improved view for a visual query in a mobile location or object search are provided. In some embodiments, methods for automatically determining an improved view for a visual query in a mobile location or object search system include obtaining at least one data set based on a prior visual query, wherein the at least one data set includes at least a top location or object and one or more other locations or objects; retrieving at least one distinctiveness measurement for one or more locations or objects in the at least one data set; and determining the improved view based on the retrieved at least one distinctiveness measurement.

    Abstract translation: 提供了用于在移动位置或对象搜索中自动确定视觉查询的改进视图的系统和方法。 在一些实施例中,用于自动确定移动位置或对象搜索系统中的视觉查询的改进视图的方法包括基于先前的视觉查询来获得至少一个数据集,其中所述至少一个数据集包括至少顶部位置 或物体和一个或多个其他位置或物体; 检索所述至少一个数据集中的一个或多个位置或对象的至少一个独特性度量; 以及基于所检索到的至少一个独特性测量来确定改进的视图。

    NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface
    168.
    发明授权
    NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
    基于NAND的混合NVM设计,在单模并行接口中集成NAND和NOR

    公开(公告)号:US08775719B2

    公开(公告)日:2014-07-08

    申请号:US12807996

    申请日:2010-09-17

    Abstract: A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

    Abstract translation: 非易失性存储器件包括多个独立的非易失性存储器阵列,用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令,地址,设备状态和数据,用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码,并在主设备和非易失性存储设备之间传送数据代码,其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址,一个命令之前传送一个。

    High electron mobility transistor and manufacturing method thereof
    169.
    发明授权
    High electron mobility transistor and manufacturing method thereof 有权
    高电子迁移率晶体管及其制造方法

    公开(公告)号:US08710551B2

    公开(公告)日:2014-04-29

    申请号:US13597599

    申请日:2012-08-29

    CPC classification number: H01L29/66462 H01L29/2003 H01L29/41766 H01L29/7787

    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

    Abstract translation: 本发明公开了一种高电子迁移率晶体管(HEMT)及其制造方法。 HEMT包括半导体层,半导体层上的势垒层,阻挡层上的压电层,压电层上的栅极,栅极两侧的源极和漏极,其中半导体的每个带隙 层,阻挡层和压电层部分但不完全与其它两个带隙重叠。 栅极形成为用于接收栅极电压。 二维电子气体(2DEG)形成在半导体层和阻挡层之间的结的一部分中,但不在压电层的至少一部分下方,其中2DEG电连接到源极和漏极。

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