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公开(公告)号：US11486928B2
公开(公告)日：2022-11-01
申请号：US17159511
申请日：2021-01-27
Inventor： Ignazio Pisello , Yu Yong Wang , Dario Arena , Qi Yu Liu
IPC: G01R31/3185 , G01R31/317 , G06F1/06
Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.
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公开(公告)号：US11303271B2
公开(公告)日：2022-04-12
申请号：US16991126
申请日：2020-08-12
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Hong Wu Lin
Abstract: A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.
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公开(公告)号：US20220085848A1
公开(公告)日：2022-03-17
申请号：US17024270
申请日：2020-09-17
Inventor： Wenhe Zhao , Jiasheng Wang
Abstract: A method for modulating a signal including operating a circuit in a first arrangement during a first operating interval and switching the circuit between the first arrangement and a second arrangement during a first modulation interval to vary a load on the circuit to produce a first amplitude shift keying (ASK) signal. The method further includes detecting a voltage on the circuit crossing a threshold level and operating the circuit in the second arrangement during a second operating interval. The method also includes switching the circuit between the second arrangement and the first arrangement during a second modulation interval to vary the load on the circuit to produce a second ASK signal.
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公开(公告)号：US11095170B1
公开(公告)日：2021-08-17
申请号：US16931111
申请日：2020-07-16
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Jiasheng Wang
Abstract: A system and method for improving ASK packet transfer reliability and power dissipation efficiency at light-load or no-load conditions of a receiving device is provided. In an embodiment, the receiving device includes a dissipating element coupled to a rectifier. The dissipating element is connected to a reference voltage at a first duration corresponding to a transmission of the ASK packet. The dissipating element is disconnected from the reference voltage a second duration corresponding to an end of the transmission of the ASK packet.
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公开(公告)号：US10944366B2
公开(公告)日：2021-03-09
申请号：US16291971
申请日：2019-03-04
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： Ru Feng Du , XiangSheng Li
Abstract: In an embodiment, a class-AB amplifier includes: an output stage that includes a pair of half-bridges configured to be coupled to a load; and a current sensing circuit coupled to a first half-bridge of the pair of half-bridges. The current sensing circuit includes a resistive element and is configured to sense a load current flowing through the load by: mirroring a current flowing through a first transistor of the first half-bridge to generate a mirrored current, flowing the mirrored current through the resistive element, and sensing the load current based on a voltage of the resistive element.
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Patent Agency Ranking
公开(公告)号：US10917086B2
公开(公告)日：2021-02-09
申请号：US16410857
申请日：2019-05-13
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Jian Wen , Hong Xia Li , Mei Yang
IPC: H03K17/687 , H03F3/45 , G01R31/30
Abstract: In an embodiment, a power switch controller for driving a back-to-back power switch includes: an amplifier having a supply terminal configured to receive a supply voltage, an output configured to be coupled to a gate terminal of the back-to-back power switch, a first input configured to be coupled a source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier.
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公开(公告)号：US10911092B2
公开(公告)日：2021-02-02
申请号：US16677422
申请日：2019-11-07
Inventor： Songfeng Zhao , Jean Pierre Proot
Abstract: A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives, over a first channel, a control signal that is transmitted in accordance with a binary protocol. The DAC also receives, over a second channel different than the first channel, data that is transmitted in accordance with a multilevel communication protocol that is different than the binary protocol. The DAC determines a plurality of first and second voltages based on the received data and identifies, based on the control signal, a time when data transmission or reception is switched between first and second antennas. In response to identifying, based on the control signal, the time when data transmission or reception is switched, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit or the determined plurality of second voltages to a second antenna tuning circuit.
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公开(公告)号：US20200076467A1
公开(公告)日：2020-03-05
申请号：US16677422
申请日：2019-11-07
Inventor： Songfeng Zhao , Jean Pierre Proot
Abstract: A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives, over a first channel, a control signal that is transmitted in accordance with a binary protocol. The DAC also receives, over a second channel different than the first channel, data that is transmitted in accordance with a multilevel communication protocol that is different than the binary protocol. The DAC determines a plurality of first and second voltages based on the received data and identifies, based on the control signal, a time when data transmission or reception is switched between first and second antennas. In response to identifying, based on the control signal, the time when data transmission or reception is switched, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit or the determined plurality of second voltages to a second antenna tuning circuit.
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公开(公告)号：US20190268034A1
公开(公告)日：2019-08-29
申请号：US16270394
申请日：2019-02-07
Inventor： Songfeng ZHAO , Jean Pierre PROOT
Abstract: A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives, over a first channel, a control signal that is transmitted in accordance with a binary protocol. The DAC also receives, over a second channel different than the first channel, data that is transmitted in accordance with a multilevel communication protocol that is different than the binary protocol. The DAC determines a plurality of first and second voltages based on the received data and identifies, based on the control signal, a time when data transmission or reception is switched between first and second antennas. In response to identifying, based on the control signal, the time when data transmission or reception is switched, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit or the determined plurality of second voltages to a second antenna tuning circuit.
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公开(公告)号：US10325584B2
公开(公告)日：2019-06-18
申请号：US14863228
申请日：2015-09-23
Inventor： Luca Molinari , Xi Chun Ma , Sandro Dalle Feste , Martino Zerbini
IPC: H04R1/10 , G10K11/178
Abstract: An active noise cancelling device including a sensor configured to convert acoustic signals into first audio signals and a speaker acoustically coupled to the sensor A control stage is configured to control the speaker based on the first audio signals to cause the speaker to produce cancelling acoustic waves that tend to suppress acoustic noise components in the acoustic signals. The control stage includes sigma-delta modulator digital filters.
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