Abstract:
Driving methods and display systems are described for operating a display panel in flash mode. In an embodiment, the driving method includes time multiplexing between at least two panel operation voltage (VOP) levels including a first VOP level and a second VOP level across all Vdd input lines to a display area, and emitting a first wavelength range from a first subpixel group during application of the first VOP level across all of the Vdd input lines and emitting a second wavelength range from a second subpixel group during application of the second VOP level across all of the Vdd input lines.
Abstract:
Display panels and encapsulation structures are described for OLED display panels, in particular. In an embodiment, a display panel includes a gate driver in panel (GIP) region, a GIP clock region within the GIP region, a pixel area region, and a VSSEL contact region laterally between an outer edge of the GIP region and the pixel area region. In some embodiments, structures are described in which capacitive coupling with the GIP clock region can be mitigated, and overlapping inorganic layers form a barrier to moisture outside of the pixel area region.
Abstract:
A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
Abstract:
Display panels including mirror pixel layouts and power rail bridges are described. In an embodiment, a display panel includes a plurality of power rail bridges joining together a subset of power rails for a plurality of adjacent mirror pixels within a row of mirror pixels.
Abstract:
An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.
Abstract:
A display may have an active area with an array of pixels to display images. An inactive area in the display may be formed from an opening in the active area. The inactive area may be enclosed by the pixels in the active area. An inactive border may run along an edge of the inactive area. A grid of positive power supply lines may be used to supply power to the pixels. Initialization voltage lines may be used to distribute initialization voltages to the pixels for use during transistor threshold voltage compensation operations. The inactive border may be free of positive power supply lines and initialization voltages lines. Control signal lines and data lines may pass through the inactive border to supply control signals and data signals respectively to the pixels. The display may have thin-film transistor circuitry with multiple layers of data lines.
Abstract:
A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
Abstract:
A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals over three control lines, may receive data over a data line, may receive a reference voltage from a reference voltage terminal, and may receive power from a pair of power supply terminals. The display driver circuitry may repeatedly operate each pixel in an initialization phase in which the drive transistor is preconditioned with on-bias stress, a data loading and threshold voltage sampling phase, and an emission phase.
Abstract:
An electronic device comprises a display and a controller. The controller is configured to determine a change in a refresh rate of the display from a first frequency to a second frequency. The controller is also configured to selectively generate a control signal configured to control emission of a light emitting diode of a display pixel of the display based on the first frequency.
Abstract:
Display driver circuitry may load data into an array of pixels via data lines. The display driver circuitry may supply control signals including scan signals to the pixels via control lines. Each pixel may have transistors and capacitor circuitry for controlling the emission of light from a light-emitting diode. A drive transistor may be coupled in series with the light-emitting diode to control the amount of current flowing through the light-emitting diode. The drive transistor may have a drive transistor gate terminal that is coupled to one of the source-drain terminals of a switching transistor. The switching transistor may have a switching transistor gate terminal that receives the scan signal. When transitioning prior to an emission phase of operation, the scan signal may have a two-step transition profile or other shape that enhances display performance by reducing dynamic effects in the switching transistor.