公开(公告)号：US11133463B2

公开(公告)日：2021-09-28

申请号：US16856631

申请日：2020-04-23

Applicant: Micron Technology, inc.

Inventor： Agostino Pirovano ,  Kolya Yastrebenetsky ,  Anna Maria Conti ,  Fabio Pellizzer

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

公开(公告)号：US20210257408A1

公开(公告)日：2021-08-19

申请号：US17306444

申请日：2021-05-03

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Agostino Pirovano ,  Lorenzo Fratin

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

公开(公告)号：US20210183947A1

公开(公告)日：2021-06-17

申请号：US17187213

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

IPC: H01L27/24 ,  H01L27/115 ,  H01L45/00

Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

公开(公告)号：US20210151109A1

公开(公告)日：2021-05-20

申请号：US17162563

申请日：2021-01-29

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano ,  Fabio Pellizzer

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses and methods for material implication operations in memory with reduced program voltages. An example apparatus can include an array of memory cells that further includes a first memory cell coupled to a first access line and to a first one of a plurality of second access lines and a second memory cell coupled to the first access line and to a second one of the plurality of second access lines. The circuitry can be configured to apply, across the second memory cell, a first voltage differential having a first polarity and a first magnitude. The first voltage differential reduces, if the second memory cell is programmed to a first data state, a magnitude of a drifted threshold voltage for programming the second memory cell to a second data state. The circuitry is further configured to apply, subsequent to the application of the first voltage differential, a first signal to the first access line. The circuitry is further configured to, while the first signal is being applied to the first access line, apply, subsequent to the application of the first voltage differential, a second voltage differential having a second polarity and the first magnitude across the first memory cell and apply a third voltage differential having the second polarity across the second memory cell. A material implication operation is performed as a result of the first, second, and third voltage differentials applied across the first and the second memory cells with a result of the material implication operation being stored on the second memory cell.

公开(公告)号：US11011582B2

公开(公告)日：2021-05-18

申请号：US16785026

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Andrea Redaelli ,  Agostino Pirovano

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.

公开(公告)号：US11005038B2

公开(公告)日：2021-05-11

申请号：US16783774

申请日：2020-02-06

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Agostino Pirovano

IPC: H01L45/00 ,  H01L27/00 ,  H01L27/24

Abstract: A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first conductive material, a second conductive material over the chalcogenide material, and a first dielectric material between the chalcogenide material and the first conductive material and between the chalcogenide material and the second conductive material. The semiconductor structure further comprises a second dielectric material on at least sidewalls of the chalcogenide material. The chalcogenide material may be substantially encapsulated by one or more dielectric materials. Related semiconductor structures and related methods are disclosed.

公开(公告)号：US10998379B2

公开(公告)日：2021-05-04

申请号：US16656824

申请日：2019-10-18

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Agostino Pirovano ,  Lorenzo Fratin

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

公开(公告)号：US20210119123A1

公开(公告)日：2021-04-22

申请号：US17088253

申请日：2020-11-03

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Anna Maria Conti ,  Agostino Pirovano

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.

公开(公告)号：US20210050521A1

公开(公告)日：2021-02-18

申请号：US16539932

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

公开(公告)号：US10910052B2

公开(公告)日：2021-02-02

申请号：US16547727

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Agostino Pirovano

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: The present disclosure includes apparatuses and methods for material implication operations in memory. An example apparatus may include a plurality of memory cells coupled to a first access line and a plurality of second access lines, and a controller coupled to the plurality of memory cells. The controller of the example apparatus may be configured to apply a first signal to the first access line, and while the first signal is being applied to the first access line, apply a second signal to a first of the plurality of memory cells via another respective one of the plurality of second access lines and apply a third signal to a second of the plurality of memory cells via another respective one of the plurality of second access lines. The material implication operation may be performed as a result of the signals (e.g., first, second, and third signals) applied and a result of the material implication operation is stored on the second of the plurality of memory cells subsequent to the application of the third signal.