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公开(公告)号：US20240407154A1
公开(公告)日：2024-12-05
申请号：US18677457
申请日：2024-05-29
Applicant: Micron Technology, Inc.
Inventor： Albert Daen Liao , Ting Zhao , Cheng Li , Ruijing Ge , Matthew Jacob Jerry , David A. Daycock , Kolya Yastrebenetsky , Kamal M. Karda
IPC: H10B12/00
Abstract: A variety of applications can include an apparatus having a memory device including digit lines isolated from each other by filling an area directly under the digit line with a dielectric material. The dielectric material can be any insulating material such as oxides or nitrides. The provision of the area directly under each digit line can be accomplished without etching out an entire layer of epitaxially grown regions for the memory cells vertically stacked in a three-dimensional array. In a three-dimensional DRAM, metal plates for capacitors can be isolated in a manner similar to the isolation of digit lines. Such processing can be scalable, which may allow for a three-dimensional DRAM to have hundreds memory cell tiers.
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公开(公告)号：US10424730B2
公开(公告)日：2019-09-24
申请号：US15893106
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Fabio Pellizzer
Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.
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公开(公告)号：US10541364B2
公开(公告)日：2020-01-21
申请号：US15893108
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US20200020855A1
公开(公告)日：2020-01-16
申请号：US16534937
申请日：2019-08-07
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Fabio Pellizzer
Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.
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公开(公告)号：US20190252607A1
公开(公告)日：2019-08-15
申请号：US15893106
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Fabio Pellizzer
CPC classification number: H01L45/1273 , G11C13/0004 , G11C13/004 , G11C2213/52 , G11C2213/71 , H01L27/2463 , H01L45/06 , H01L45/141
Abstract: Methods, systems, and devices for tapered memory cell profiles are described. A tapered profile memory cell may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a bottom surface and a top surface opposite the bottom surface. In some cases, the self-selecting memory component may taper from the bottom surface to the top surface. In other examples, the self-selecting memory component may taper from the top surface to the bottom surface. The top surface of the self-selecting memory component may be coupled to a top electrode, and the bottom surface of the self-selecting memory component may be coupled to a bottom electrode.
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Patent Agency Ranking
公开(公告)号：US20220059763A1
公开(公告)日：2022-02-24
申请号：US17480694
申请日：2021-09-21
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US11133463B2
公开(公告)日：2021-09-28
申请号：US16856631
申请日：2020-04-23
Applicant: Micron Technology, inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US20200321522A1
公开(公告)日：2020-10-08
申请号：US16856631
申请日：2020-04-23
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US20200119273A1
公开(公告)日：2020-04-16
申请号：US16706358
申请日：2019-12-06
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US20190252606A1
公开(公告)日：2019-08-15
申请号：US15893108
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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