公开(公告)号：US12283316B2

公开(公告)日：2025-04-22

申请号：US18409992

申请日：2024-01-11

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

IPC: G11C13/00

Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

公开(公告)号：US12277967B2

公开(公告)日：2025-04-15

申请号：US18586174

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli

IPC: G11C13/00 ,  G11C29/02 ,  G11C29/12

Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

公开(公告)号：US20250024761A1

公开(公告)日：2025-01-16

申请号：US18782436

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Matteo Impalà ,  Cécile Colette Solange Nail

IPC: H10N70/00 ,  G11C13/00

Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.

公开(公告)号：US12125540B2

公开(公告)日：2024-10-22

申请号：US17733474

申请日：2022-04-29

Applicant: Micron Technology, Inc.

Inventor： Mattia Robustelli ,  Innocenzo Tortorelli

IPC: G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/22 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3404

Abstract: Methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.

公开(公告)号：US20240203468A1

公开(公告)日：2024-06-20

申请号：US18593635

申请日：2024-03-01

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/1051

Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

公开(公告)号：US20240057489A1

公开(公告)日：2024-02-15

申请号：US17818617

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Matteo Impalà ,  Cécile Colette Solange Nail

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/141 ,  G11C13/003 ,  H01L45/1233

Abstract: Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.

公开(公告)号：US11798620B2

公开(公告)日：2023-10-24

申请号：US17816612

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

IPC: G11C11/34 ,  G11C11/56 ,  G11C13/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/76

Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

公开(公告)号：US11729999B2

公开(公告)日：2023-08-15

申请号：US17735810

申请日：2022-05-03

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/003 ,  G11C13/0004 ,  H10B63/34 ,  H10N70/231 ,  G11C2213/71 ,  G11C2213/75

Abstract: Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.

公开(公告)号：US20230207002A1

公开(公告)日：2023-06-29

申请号：US17647578

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

公开(公告)号：US20230058092A1

公开(公告)日：2023-02-23

申请号：US17977046

申请日：2022-10-31

Applicant: Micron Technology, Inc.

Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

IPC: G06F3/06 ,  G11C13/00 ,  G11C11/54 ,  G06N3/08

Abstract: An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.