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公开(公告)号：US12125540B2
公开(公告)日：2024-10-22
申请号：US17733474
申请日：2022-04-29
CPC分类号： G11C16/102 , G11C16/22 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3404
摘要： Methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.
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公开(公告)号：US20240203468A1
公开(公告)日：2024-06-20
申请号：US18593635
申请日：2024-03-01
IPC分类号： G11C7/10
CPC分类号： G11C7/1096 , G11C7/1051
摘要： Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).
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公开(公告)号：US20240057489A1
公开(公告)日：2024-02-15
申请号：US17818617
申请日：2022-08-09
CPC分类号： H01L45/141 , G11C13/003 , H01L45/1233
摘要： Methods, systems, and devices for random number generation based on threshold voltage randomness are described. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.
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公开(公告)号：US11798620B2
公开(公告)日：2023-10-24
申请号：US17816612
申请日：2022-08-01
发明人： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/005 , G11C2013/0052 , G11C2013/0073 , G11C2013/0092 , G11C2213/71 , G11C2213/76
摘要： Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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公开(公告)号：US11729999B2
公开(公告)日：2023-08-15
申请号：US17735810
申请日：2022-05-03
CPC分类号： H10B63/845 , G11C13/003 , G11C13/0004 , H10B63/34 , H10N70/231 , G11C2213/71 , G11C2213/75
摘要： Methods, systems, and devices for a capacitive pillar architecture for a memory array are described. An access line within a memory array may be, include, or be coupled with a pillar. The pillar may include an exterior electrode, such as a hollow exterior electrode, surrounding an inner dielectric material that may further surround an interior, core electrode. The interior electrode may be maintained at a voltage level during at least a portion of an access operation for a memory cell coupled with the pillar. Such a pillar structure may increase a capacitance of the pillar, for example, based on a capacitive coupling between the interior and exterior electrodes. The increased capacitance may provide benefits associated with operating the memory array, such as increased memory cell programming speed, programming reliability, and read disturb immunity.
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公开(公告)号：US20230207002A1
公开(公告)日：2023-06-29
申请号：US17647578
申请日：2022-01-10
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71
摘要： Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
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公开(公告)号：US20230058092A1
公开(公告)日：2023-02-23
申请号：US17977046
申请日：2022-10-31
摘要： An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.
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公开(公告)号：US11489117B2
公开(公告)日：2022-11-01
申请号：US17308444
申请日：2021-05-05
发明人： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Andrea Redaelli , Innocenzo Tortorelli
摘要： A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.
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公开(公告)号：US11487464B2
公开(公告)日：2022-11-01
申请号：US16503015
申请日：2019-07-03
摘要： An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.
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公开(公告)号：US11380391B2
公开(公告)日：2022-07-05
申请号：US17104547
申请日：2020-11-25
摘要： In an example, an apparatus can include an array of memory cells and a neural memory unit controller coupled to the array of memory cells and configured to assert respective voltage pulses during a first training interval to memory cells of the array to change respective threshold voltages of the memory cells from voltages associated with a reset state to effectuate respective synaptic weight changes. The neural memory unit controller can be configured to initiate a sleep interval, during which no pulses are applied to the memory cells, to effectuate respective voltage drifts in the changed respective threshold voltages of the memory cells from a voltage associated with a set state toward the voltage associated with the reset state, and determine an output of the memory cells responsive to the respective voltage drifts in the changed respective threshold voltages after the sleep interval.
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