公开(公告)号：US20130290801A1

公开(公告)日：2013-10-31

申请号：US13890781

申请日：2013-05-09

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318536 ,  G01R31/318544

Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US20130285701A1

公开(公告)日：2013-10-31

申请号：US13890856

申请日：2013-05-09

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: H03K19/0175

CPC classification number: H03K19/01759 ,  H04L25/0272

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

公开(公告)号：US08572446B2

公开(公告)日：2013-10-29

申请号：US13870238

申请日：2013-04-25

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  G01R31/26

CPC classification number: G01R31/2851 ,  G01R31/318566 ,  G01R31/3187 ,  G01S19/24

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract translation: 测试控制器将测试激励信号并行地施加到晶片上的多个管芯的输入焊盘。 测试控制器还将编码的测试响应信号并行地应用于多个管芯的输出焊盘。 编码的测试响应信号在芯片上解码，并与通过将测试激励信号应用于芯片上的核心电路产生的核心测试响应信号进行比较。 该比较产生加载到IEEE 1149.1扫描路径的扫描单元中的通过/失败信号。 然后可以将通过/失败信号扫描出模具以确定测试结果。

公开(公告)号：US20130246872A1

公开(公告)日：2013-09-19

申请号：US13891760

申请日：2013-05-10

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/318555 ,  G01R31/3177 ,  G01R31/318572

Abstract: A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.

Abstract translation: 在集成电路内选择替代测试电路的过程使得测试访问端口成为可能。 扫描测试指令数据被加载到测试访问端口TAP的指令寄存器中，指令数据包括用于选择备用测试电路的信息。 在加载结束时执行Update-IR指令更新操作，以从指令寄存器输出扫描测试控制信号。 锁定信号变为活动状态以禁用测试访问端口并启用扫描测试电路。

公开(公告)号：US20130232388A1

公开(公告)日：2013-09-05

申请号：US13858625

申请日：2013-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318544 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318575

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

公开(公告)号：US08522094B2

公开(公告)日：2013-08-27

申请号：US13677795

申请日：2012-11-15

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318572 ,  G06F1/10

Abstract: Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.

Abstract translation: 连接电路将扫描测试端口（STP）电路耦合到测试访问端口（TAP）电路。 连接电路具有连接到扫描电路的输入，控制来自TAP电路的输出引线，选择输入引线和时钟输入引线。 连接电路具有连接到STP电路的扫描使能（SE）输入引线，捕捉选择（CS）输入引线和扫描时钟（CK）输入引线的输出。 连接电路包括多路复用器，其具有与来自TAP电路的时钟选择引线连接的控制输入，与功能时钟引线连接的输入，与时钟输入引线连接的输入，与来自 TAP电路，OFF引线和与扫描时钟输入引线相连的输出。

公开(公告)号：US20130145226A1

公开(公告)日：2013-06-06

申请号：US13757334

申请日：2013-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318536

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

公开(公告)号：US20130103996A1

公开(公告)日：2013-04-25

申请号：US13712418

申请日：2012-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318572

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Abstract translation: 集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。 这些端口的访问和控制是一个测试链接模块。 集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。 每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。 测试链接模块也可用于仿真。

公开(公告)号：US20240345154A1

公开(公告)日：2024-10-17

申请号：US18754683

申请日：2024-06-26

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/26 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/2607 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318552 ,  G01R31/318594

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

公开(公告)号：US20240337691A1

公开(公告)日：2024-10-10

申请号：US18744322

申请日：2024-06-14

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/273

CPC classification number: G01R31/318335 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318547 ,  G06F11/2733

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.