公开(公告)号：US10472731B2

公开(公告)日：2019-11-12

申请号：US15497182

申请日：2017-04-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/31 ,  C25F3/12 ,  H01L21/311 ,  H01L23/525 ,  H01L23/00

Abstract: A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon. A liner and an etching stop layer are formed at least covering a top surface of the fuse metal. A dielectric layer is formed on the substrate and a passivation layer is formed over the dielectric layer. A pad opening and a fuse opening are defined in the passivation layer. A first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening to expose a top surface of the pad metal from the pad opening and an upper surface of the etching stop layer from the fuse opening respectively. A second etching step is performed to remove the etching stop layer from the fuse opening until an upper surface of the liner is exposed.

公开(公告)号：US10431679B2

公开(公告)日：2019-10-01

申请号：US15942568

申请日：2018-04-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L29/00 ,  H01L29/78 ,  H01L21/4757 ,  H01L21/02 ,  H01L21/762 ,  H01L27/108 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.

公开(公告)号：US10396048B2

公开(公告)日：2019-08-27

申请号：US15854785

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chin-Hsin Chiu

IPC: H01L23/485 ,  H01L23/00 ,  H01L21/66 ,  H01L23/525 ,  H01L21/768 ,  H01L23/62 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/31

Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.

公开(公告)号：US10381239B2

公开(公告)日：2019-08-13

申请号：US16104948

申请日：2018-08-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/20 ,  H01L21/311 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes following steps. First of all, a substrate is provided, and a stacked structure is formed on the substrate. Then, a patterned silicon-containing mask layer is formed on the stacked structure, and the stacked structure is partially removed through the patterned silicon-containing mask layer, to form plural openings in the stacked structure. Following these, a bromine covering process is performed, to form a bromide layer on a portion of the patterned silicon-containing mask layer, and a bromide sublimation process is then performed, to completely remove the bromide layer.

公开(公告)号：US20190181014A1

公开(公告)日：2019-06-13

申请号：US16167435

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033

Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.

公开(公告)号：US20190109013A1

公开(公告)日：2019-04-11

申请号：US16104948

申请日：2018-08-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/311 ,  H01L49/02

CPC classification number: H01L21/31144 ,  H01L28/40

Abstract: A method of forming a semiconductor device includes following steps. First of all, a substrate is provided, and a stacked structure is formed on the substrate. Then, a patterned silicon-containing mask layer is formed on the stacked structure, and the stacked structure is partially removed through the patterned silicon-containing mask layer, to form plural openings in the stacked structure. Following these, a bromine covering process is performed, to form a bromide layer on a portion of the patterned silicon-containing mask layer, and a bromide sublimation process is then performed, to completely remove the bromide layer.

公开(公告)号：US10256312B1

公开(公告)日：2019-04-09

申请号：US15886812

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Yi-Ching Chang

IPC: H01L29/423 ,  H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor structure includes a contact plug located on a barrier layer in a contact hole; a first conductive feature integrally formed with the contact plug on the barrier layer; a second conductive feature disposed on the interlayer dielectric layer; and a gap between the first and second conductive features. The gap includes a vertical trench recessed into the interlayer dielectric layer, and a discontinuity in the barrier layer. The discontinuity extends below the second conductive feature to form an undercut structure.

公开(公告)号：US10249629B1

公开(公告)日：2019-04-02

申请号：US15876220

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Chiang Chen ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Chieh-Te Chen ,  Hsien-Shih Chu

IPC: H01L27/108 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/3213

Abstract: The present invention provides a method for forming buried word lines. Firstly, a substrate is provided, having a plurality of shallow trench isolations disposed therein, next, a plurality of first patterned material layers are formed on the substrate, a plurality of first recesses are disposed between every two adjacent first patterned material layers, a second patterned material layer is formed in the first recesses, and using the first patterned material layers and the second patterned material layer as the protect layers, and a first etching process is then performed, to form a plurality of second recesses in the substrate.

公开(公告)号：US20190080961A1

公开(公告)日：2019-03-14

申请号：US16188237

申请日：2018-11-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/108 ,  H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/02 ,  H01L23/535

Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate is provided and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.

公开(公告)号：US20190080959A1

公开(公告)日：2019-03-14

申请号：US15974664

申请日：2018-05-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033

Abstract: The present invention provides a method for fabricating a semiconductor structure. A multilayer structure on is formed a substrate, the multilayer structure includes at least a first dielectric layer, a second dielectric layer and an amorphous silicon layer, next, a first etching step is performed, to forma first recess in the amorphous silicon layer and in the second dielectric layer, parts of the first dielectric layer is exposed by the first recess, afterwards, a hard mask layer is formed in the first recess, a second etching step is then performed to remove the hard mask layer and to expose a surface of the first dielectric layer, and a third etching step is performed with the remaining hard mask layer, to remove a portion of the first dielectric layer, so as to form a second recess in the first dielectric layer.