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公开(公告)号：US20190318929A1
公开(公告)日：2019-10-17
申请号：US15972223
申请日：2018-05-06
发明人： Yu-Chen Chuang , Fu-Che Lee , Ming-Feng Kuo , Cheng-Yu Wang , Hsien-Shih Chu , Li-Chiang Chen
IPC分类号： H01L21/033
摘要： A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.
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2.发明授权公开(公告)号：US10170362B2
公开(公告)日：2019-01-01
申请号：US15472295
申请日：2017-03-29
发明人： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Fu-Che Lee , Ming-Feng Kuo
IPC分类号： H01L23/52 , H01L21/768 , H01L21/762 , H01L21/311 , H01L21/02 , H01L23/535 , H01L29/06 , H01L23/528 , H01L27/108
摘要： The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.
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公开(公告)号：US20180277354A1
公开(公告)日：2018-09-27
申请号：US15497182
申请日：2017-04-25
发明人： Feng-Yi Chang , Fu-Che Lee , Ming-Feng Kuo
CPC分类号： C25F3/12 , H01L21/31116 , H01L23/5258 , H01L24/00
摘要： A method of forming a semiconductor structure is disclosed. A substrate is provided with a pad metal and a fuse metal formed thereon. A liner and an etching stop layer are formed at least covering a top surface of the fuse metal. A dielectric layer is formed on the substrate and a passivation layer is formed over the dielectric layer. A pad opening and a fuse opening are defined in the passivation layer. A first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening to expose a top surface of the pad metal from the pad opening and an upper surface of the etching stop layer from the fuse opening respectively. A second etching step is performed to remove the etching stop layer from the fuse opening until an upper surface of the liner is exposed.
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公开(公告)号：US20180108563A1
公开(公告)日：2018-04-19
申请号：US15384940
申请日：2016-12-20
发明人： Chieh-Te Chen , Hsien-Shih Chu , Ming-Feng Kuo , Fu-Che Lee , Chien-Ting Ho , Chiung-Lin Hsu , Feng-Yi Chang , Yi-Wang Zhan , Li-Chiang Chen , Chien-Cheng Tsai , Chin-Hsin Chiu
IPC分类号： H01L21/762 , H01L21/308
CPC分类号： H01L21/76224 , H01L21/3081 , H01L21/762
摘要： A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
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公开(公告)号：US09887088B1
公开(公告)日：2018-02-06
申请号：US15452743
申请日：2017-03-08
发明人： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Ming-Feng Kuo , Li-Chiang Chen
IPC分类号： H01L21/28 , H01L21/3213
CPC分类号： H01L21/28088 , H01L21/32135
摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; forming a barrier layer in the trench; forming a conductive layer on the barrier layer; performing a first etching process to remove part of the conductive layer; and performing a second etching process to remove part of the barrier layer. Preferably, the second etching process comprises a non-plasma etching process.
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公开(公告)号：US10199258B2
公开(公告)日：2019-02-05
申请号：US15384940
申请日：2016-12-20
发明人： Chieh-Te Chen , Hsien-Shih Chu , Ming-Feng Kuo , Fu-Che Lee , Chien-Ting Ho , Chiung-Lin Hsu , Feng-Yi Chang , Yi-Wang Zhan , Li-Chiang Chen , Chien-Cheng Tsai , Chin-Hsin Chiu
IPC分类号： H01L21/762 , H01L21/308
摘要： A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
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公开(公告)号：US20180342425A1
公开(公告)日：2018-11-29
申请号：US16038196
申请日：2018-07-18
发明人： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Ming-Feng Kuo , Li-Chiang Chen
IPC分类号： H01L21/8234 , H01L27/108
摘要： A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.
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公开(公告)号：US10153165B1
公开(公告)日：2018-12-11
申请号：US15868915
申请日：2018-01-11
发明人： Feng-Yi Chang , Fu-Che Lee , Ming-Feng Kuo , Chien-Cheng Tsai
IPC分类号： H01L21/033 , H01L21/311 , H01L21/308 , H01L21/3213 , H01L21/027
摘要： The present invention pertains to a patterning method. By taking advantage of the etching loading effect due to different pattern densities in the memory cell region and the peripheral region, the first hard mask is not masked when anisotropically etching the first hard mask within the memory cell region.
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公开(公告)号：US10062613B1
公开(公告)日：2018-08-28
申请号：US15611759
申请日：2017-06-01
发明人： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Ming-Feng Kuo , Li-Chiang Chen
IPC分类号： H01L27/108 , H01L29/51 , H01L29/78 , H01L21/8234
CPC分类号： H01L21/823456 , H01L21/82345 , H01L27/10823 , H01L27/10876 , H01L27/10891
摘要： A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate; forming a first work function metal layer in the first trench and the second trench; forming a patterned mask to cover the second trench; removing the first work function metal layer from the first trench; forming a second work function metal layer in the first trench and the second trench; and forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.
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公开(公告)号：US10937701B2
公开(公告)日：2021-03-02
申请号：US16038196
申请日：2018-07-18
发明人： Feng-Yi Chang , Shih-Fang Tzou , Yu-Cheng Tung , Ming-Feng Kuo , Li-Chiang Chen
IPC分类号： H01L27/108 , H01L21/8234
摘要： A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.
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