Methods and systems for sorting unaddressed items
    171.
    发明申请
    Methods and systems for sorting unaddressed items 有权
    排除未编址项目的方法和系统

    公开(公告)号:US20050230290A1

    公开(公告)日:2005-10-20

    申请号:US10952818

    申请日:2004-09-30

    IPC分类号: B07C3/00 B07C5/00 G06K9/00

    CPC分类号: B07C3/00 Y10S209/90

    摘要: Systems and methods for sorting a plurality of unaddressed items may comprise receiving delivery point address data. Furthermore, systems and methods for sorting a plurality of unaddressed items may comprise sorting the plurality of unaddressed items based on the delivery point address data. The plurality of unaddressed items may be sorted in an order in which they are to be delivered within a delivery zone specified by the delivery point address data.

    摘要翻译: 用于排序多个未寻址的物品的系统和方法可以包括接收递送点地址数据。 此外,用于排序多个未寻址项目的系统和方法可以包括基于递送点地址数据对多个未寻址项目进行排序。 多个未解决的项目可以按照它们在由递送点地址数据指定的递送区域内被递送的顺序进行排序。

    UV sterilisation air-flow chamber
    172.
    发明申请
    UV sterilisation air-flow chamber 审中-公开
    UV灭菌空气流通室

    公开(公告)号:US20050047975A1

    公开(公告)日:2005-03-03

    申请号:US10911008

    申请日:2004-08-04

    申请人: Wai Tang Wilson Wong

    发明人: Wai Tang Wilson Wong

    IPC分类号: A61L9/20 A61L9/18

    CPC分类号: A61L9/20

    摘要: A sterilisation chamber includes an elongate housing, an air inlet port adjacent to one end of the housing, an air outlet port adjacent to the other end of the housing, and an elongate ultraviolet fluorescent tube mounted within the housing and extending from the inlet port to the outlet port. Air passing through the housing from one end to the other encounters ultraviolet light emitted from the fluorescent tube en route from the inlet port to the outlet port.

    摘要翻译: 消毒室包括细长壳体,与壳体的一端相邻的空气入口端口,与壳体的另一端相邻的空气出口端口和安装在壳体内并从入口端口延伸到其中的细长紫外线荧光灯管 出口口。 从一端到另一端穿过壳体的空气在从入口到出口的途中遇到从荧光管发射的紫外线。

    Overvoltage-tolerant interface for integrated circuits
    173.
    发明授权
    Overvoltage-tolerant interface for integrated circuits 失效
    集成电路的过压容限接口

    公开(公告)号:US6147511A

    公开(公告)日:2000-11-14

    申请号:US863886

    申请日:1997-05-27

    摘要: An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.

    摘要翻译: 一种用于直接与在输入/输出驱动器的电源电压(817)之上的焊盘(820)处的电压直接接口的输入/输出驱动器。 这可以被称为“过电压状态”。例如,如果电源电压为3.3V,则可以在输入/输出驱动器的焊盘处提供5V电压信号。 输入/输出驱动器将容忍该电压电平并防止漏电流路径。 这将提高集成电路的性能,可靠性和使用寿命。 输入/输出驱动器包括用于防止泄漏电流路径的阱偏压发生器(1002)。

    Circuitry for a low internal voltage integrated circuit
    174.
    发明授权
    Circuitry for a low internal voltage integrated circuit 失效
    低内部集成电路的电路

    公开(公告)号:US6025737A

    公开(公告)日:2000-02-15

    申请号:US863876

    申请日:1997-05-27

    摘要: A technique and circuitry for interfacing an integrated circuit manufactured using technology compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, the integrated circuit is fabricated using technology compatible with an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage. The input and output signals to and from the integrated circuit will be compatible with the external supply level. The integrated circuit may include a voltage down converter (1330) and level shifter (1317).

    摘要翻译: 一种技术和电路,用于使用与一个电压电平兼容的技术制造的集成电路与与不同电压电平兼容的其他集成电路进行接口。 特别地,使用与内部电源电压相兼容的技术来制造集成电路。 在外部,集成电路将与外部电源电压接口,高于内部电源电压。 来往于集成电路的输入和输出信号将与外部电源电平兼容。 集成电路可以包括电压降压转换器(1330)和电平移位器(1317)。

    Method of fabricating integrated circuits
    175.
    发明授权
    Method of fabricating integrated circuits 失效
    集成电路的制造方法

    公开(公告)号:US5693540A

    公开(公告)日:1997-12-02

    申请号:US656448

    申请日:1996-05-31

    摘要: A method of fabricating integrated circuits is provided that allows new integrated circuits to be fabricated with reduced die areas and reduced power consumptions relative to old integrated circuits. The new circuits are interchangeable with the old integrated circuits, because the delay times for the data pathways through the new circuits are the same as the delay times for the data pathways through the old circuits. A family of new circuits, each of which is compatible with a corresponding one of a series of old circuits, can be fabricated using a common circuit layout. Each new circuit is associated with a parameter value that governs the delay time of a component in a data pathway through the circuit and ensures that the new circuit is compatible with the corresponding old circuit.

    摘要翻译: 提供了一种制造集成电路的方法,其允许以相对于旧的集成电路减少的芯片面积和降低的功率消耗来制造新的集成电路。 新电路可以与旧的集成电路互换,因为通过新电路的数据通路的延迟时间与通过旧电路的数据通道的延迟时间相同。 可以使用公共电路布局来制造每一个与一系列旧电路中的相应一个电路兼容的新电路系列。 每个新电路与控制通过电路的数据通路中的部件的延迟时间的参数值相关联,并确保新电路与相应的旧电路兼容。