Slicer with large input common mode range
    171.
    发明授权
    Slicer with large input common mode range 有权
    切片机具有大输入共模范围

    公开(公告)号:US07248081B2

    公开(公告)日:2007-07-24

    申请号:US11204113

    申请日:2005-08-16

    CPC classification number: H03K5/086

    Abstract: A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter for inverting the initial output signal to provide a final output signal. The input stage includes a first circuit including a plurality of transistors and a complimentary circuit including a plurality of transistors. When a low common mode input voltage causes the transistors of the first circuit to turn off, the transistors of the complimentary circuit will take over to accomplish the same task as the first circuit.

    Abstract translation: 提供了具有大输入共模范围的切片机。 限幅器包括耦合以接收输入信号的输入级,用于为输入级提供电流的电流源,耦合到输入级的自偏置负载以提供初始输出信号,以及用于反相初始输出信号的反相器 以提供最终的输出信号。 输入级包括包括多个晶体管的第一电路和包括多个晶体管的补偿电路。 当低共模输入电压导致第一电路的晶体管截止时,互补电路的晶体管将接管以完成与第一电路相同的任务。

    On-chip capacitor structure with adjustable capacitance
    172.
    发明申请
    On-chip capacitor structure with adjustable capacitance 失效
    具有可调电容的片上电容结构

    公开(公告)号:US20070075350A1

    公开(公告)日:2007-04-05

    申请号:US11411648

    申请日:2006-04-26

    Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

    Abstract translation: 至少第一电容器形成在衬底上并连接到差分电路的第一差分节点,并且第一电容器可以是可变电容的。 第二电容器形成在衬底上并连接到差分电路的第二差分节点,并且第二电容器也可以是可变的。 第三电容器连接在第一差分节点和第二差分节点之间,并且至少部分地形成在第一电容器的上方。 以这种方式,可以在衬底上减小第一电容器和/或第二电容器的尺寸,并且可以响应于一个或多个电路的可变特性来调整第一和/或第二电容器的电容 差分电路的组件。

    Analog FSK modulator for a radio transmitter
    174.
    发明授权
    Analog FSK modulator for a radio transmitter 失效
    用于无线电发射机的模拟FSK调制器

    公开(公告)号:US07103113B2

    公开(公告)日:2006-09-05

    申请号:US10183582

    申请日:2002-06-26

    Applicant: Hooman Darabi

    Inventor: Hooman Darabi

    CPC classification number: H04L27/12 H03K7/06

    Abstract: A transceiver includes a transmitter portion with an analog modulator that modulates data using frequency shift keyed (FSK) modulation techniques to increase efficiency, reduce power consumption, and reduce IC real estate in comparison to current digital FSK modulation circuits. The analog modulator comprises a loop that includes a pair of integrators and a pair of mixers. In at least one embodiment, the pair of mixers comprises switches that control a polarity of a modulated output signal that is produced to an up-conversion module for up-conversion to RF. The up-conversion module, then, when mixing the modulated output signal with a local oscillation signal, produces an output having one of two possible frequencies wherein the frequencies are a function of the polarity of the modulated output signal. In one embodiment of the invention, the analog modulator comprises differential circuitry, including a plurality of differential switches for cross-connecting input signals to one of a pair of inputs of an amplifier within each of a pair of integrators. Thus, the polarity of the modulated output signal is, at least in part, a function of whether a given signal is input to a positive or a negative terminal of the amplifier within the pair of integrators.

    Abstract translation: 收发器包括具有模拟调制器的发射器部分,其使用频移键控(FSK)调制技术来调制数据,以提高效率,降低功耗,并且与当前数字FSK调制电路相比降低IC的实际值。 模拟调制器包括一个包括一对积分器和一对混频器的回路。 在至少一个实施例中,该对混频器包括控制向上转换模块产生的调制输出信号的极性的开关,用于向RF转换。 然后,上变频模块在将调制的输出信号与本地振荡信号混合时产生具有两个可能频率之一的输出,其中频率是调制输出信号的极性的函数。 在本发明的一个实施例中,模拟调制器包括差分电路,包括多个差分开关,用于将输入信号交叉连接到一对积分器内的放大器的一对输入之一。 因此,调制输出信号的极性至少部分地是给定信号是否被输入到该对积分器内的放大器的正或负端的功能。

    Method and system for a second order input intercept point (IIP2) correction
    175.
    发明申请
    Method and system for a second order input intercept point (IIP2) correction 有权
    二阶输入截点(IIP2)校正方法和系统

    公开(公告)号:US20060094387A1

    公开(公告)日:2006-05-04

    申请号:US10977000

    申请日:2004-10-29

    Applicant: Hooman Darabi

    Inventor: Hooman Darabi

    Abstract: In RF transceivers a method and system for process, voltage, and temperature (PVT) measurement and calibration are provided. A nominal DC offset current may be generated at a nominal temperature and may be based on a calibration voltage. A nominal transconductance parameter may be determined based on the nominal DC offset current and the calibration voltage. The nominal transconductance may be stored and may be utilized to determine temperature and process conditions during operation. In another embodiment, a plurality of DC offset currents may be generated at different temperatures and these generated DC offset currents may be based on a calibration voltage. The calibration voltage may be constant over the range of temperatures. Transconductance parameters may be determined based on the DC offset currents and the calibration voltage. The transconductance parameters may be stored and may be utilized to determine temperature and process conditions during operation.

    Abstract translation: 在RF收发器中,提供了一种用于过程,电压和温度(PVT)测量和校准的方法和系统。 标称直流偏移电流可以在标称温度下产生,并且可以基于校准电压。 标称跨导参数可以基于标称直流偏移电流和校准电压来确定。 标称跨导可以被存储并且可以用于在操作期间确定温度和工艺条件。 在另一个实施例中,可以在不同温度下产生多个DC偏移电流,并且这些产生的DC偏移电流可以基于校准电压。 校准电压在温度范围内可能是恒定的。 可以基于DC偏移电流和校准电压来确定跨导参数。 可以存储跨导参数并且可以用于确定操作期间的温度和工艺条件。

    Method and system for a divide by N circuit with dummy load for multiband radios
    176.
    发明申请
    Method and system for a divide by N circuit with dummy load for multiband radios 有权
    用于多频无线电的N电路与虚拟负载分离的方法和系统

    公开(公告)号:US20060091919A1

    公开(公告)日:2006-05-04

    申请号:US10977631

    申请日:2004-10-29

    Applicant: Hooman Darabi

    Inventor: Hooman Darabi

    CPC classification number: H04B1/406

    Abstract: Certain embodiments of the invention provide a method and system for symmetrically loading a divider circuit for multiband receivers. The method may comprise coupling a second divider circuit to an I component output signal of a first divider circuit and coupling a dummy load to a Q component output signal of the first divider circuit. The dummy load may comprise a load that may be equivalent to the second divider circuit. At least an I component output signal may be generated from the second divider circuit. At least a Q component signal may be generated from the second divider circuit. At least an I component signal generated from the first divider circuit may be received by the second divider circuit. At least a Q component signal generated from the first divider circuit may be received by a dummy load.

    Abstract translation: 本发明的某些实施例提供了一种用于对称加载用于多频带接收机的分频器电路的方法和系统。 该方法可以包括将第二分频器电路耦合到第一分频器电路的I分量输出信号,并将虚拟负载耦合到第一分频器电路的Q分量输出信号。 虚拟负载可以包括可以等效于第二分频器电路的负载。 至少可以从第二分频器电路产生I分量输出信号。 可以从第二分频器电路产生至少一个Q分量信号。 至少从第一分频电路产生的I分量信号可以由第二分频电路接收。 至少从第一分频电路产生的Q分量信号可以由虚拟负载接收。

    LNA gain adjustment for intermodulation interference reduction
    178.
    发明授权
    LNA gain adjustment for intermodulation interference reduction 有权
    LNA增益调整用于互调干扰减少

    公开(公告)号:US06961552B2

    公开(公告)日:2005-11-01

    申请号:US10138752

    申请日:2002-05-03

    CPC classification number: H03G3/3052 H04B1/406

    Abstract: The radio receiver includes a low noise amplifier that amplifies a received signal to one of three different gain settings. One gain setting is maximum amplification, a second gain setting is 6 dB below maximum amplification and a third gain setting is 32 dB below maximum amplification. In the case of the third setting, the low noise amplifier actually attenuates the received signal by 6 dB. The radio receiver includes a pair of received signal strength indicators that provide received signal strength indications to logic circuitry. Responsive to the received signal strength indications, the logic circuitry generates control commands to the low noise amplifier to prompt it to amplify at one of the three specified levels. Generally, if the received signal has a gain level that exceeds a specified threshold, the low noise amplifier actually attenuates the received signal; otherwise, the level of amplification that is actually provided is a function of the presence of intermodulation interference.

    Abstract translation: 无线电接收机包括一个低噪声放大器,将接收到的信号放大到三种不同的增益设置之一。 一个增益设置是最大放大倍数,第二增益设置比最大放大6 dB,第三增益设置低于最大放大32 dB。 在第三设置的情况下,低噪声放大器实际上将接收信号衰减6dB。 无线电接收机包括一对接收的信号强度指示器,其向逻辑电路提供接收到的信号强度指示。 响应于接收的信号强度指示,逻辑电路产生对低噪声放大器的控制命令,以提示其在三个指定电平之一上放大。 通常,如果接收信号具有超过规定阈值的增益电平,则低噪声放大器实际上衰减接收信号; 否则,实际提供的放大级别是互调干扰的存在的函数。

    CMOS-based receiver for communications applications
    179.
    发明申请
    CMOS-based receiver for communications applications 有权
    基于CMOS的接收机,用于通信应用

    公开(公告)号:US20050237100A1

    公开(公告)日:2005-10-27

    申请号:US10832237

    申请日:2004-04-27

    Abstract: A receiver and receiver front end having multiple independent differential inputs, multiple independent differential low-noise amplifiers, and two sets of double-balanced IQ mixers. The double-balanced mixers include cross-coupled PMOS devices that dynamically inject current at zero-crossing points to cancel out tail currents in the mixers. Also, methods of operating the above-discussed receiver and receiver front end.

    Abstract translation: 具有多个独立差分输入的接收器和接收器前端,多个独立的差分低噪声放大器和两组双平衡IQ混频器。 双平衡混频器包括跨耦合PMOS器件,其在过零点动态地注入电流以抵消混频器中的尾电流。 另外,操作上述接收机和接收机前端的方法。

    Analog peak detection circuitry for radio receivers

    公开(公告)号:US20050197092A1

    公开(公告)日:2005-09-08

    申请号:US11114544

    申请日:2005-04-26

    Applicant: Hooman Darabi

    Inventor: Hooman Darabi

    CPC classification number: H03G3/3052 H04B1/406

    Abstract: A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors that are introduced by crystals within filters and other devices. A voltage follower and a current mirror in which a MOSFET coupled to an output node produces a voltage across its gate to source terminals whose value is a function of a sum of the gate to source voltages of two MOSFET devices that receive a logarithm of an I modulated channel and a logarithm of a Q modulated channel, respectively.

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