公开(公告)号：US20190005335A1

公开(公告)日：2019-01-03

申请号：US15638142

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

IPC: G06K9/00 ,  G06T7/20 ,  G06T1/00

Abstract: A computer vision system is provided that includes an image generation device configured to capture consecutive two dimensional (2D) images of a scene, a first memory configured to store the consecutive 2D images, a second memory configured to store a growing window of consecutive rows of a reference image and a growing window of consecutive rows of a current image, wherein the reference image and the current image are a pair of consecutive 2D images stored in the first memory, a third memory configured to store a sliding window of pixels fetched from the growing window of the reference image, wherein the pixels in the sliding window are stored in tiles, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for the pair of consecutive 2D images, wherein the DOFE uses the sliding window as a search window for pixel correspondence searches.

公开(公告)号：US20180357513A1

公开(公告)日：2018-12-13

申请号：US16108237

申请日：2018-08-22

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Manu Mathew ,  Chaitanya Satish Ghone

IPC: G06K9/62 ,  G06K9/46

CPC classification number: G06K9/4628 ,  G06K9/522 ,  G06K9/6271

Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.

公开(公告)号：US20180192060A1

公开(公告)日：2018-07-05

申请号：US15853474

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/117 ,  H04N19/86

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/186 ,  H04N19/82 ,  H04N19/86

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US20180189105A1

公开(公告)日：2018-07-05

申请号：US15396153

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/50 ,  G06F9/46

CPC classification number: G06F9/5027 ,  G06F9/4812 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node is configured to execute a task, and a hardware thread scheduler coupled to the plurality of hardware data processing nodes, the hardware thread scheduler configurable to concurrently execute a first thread of tasks and a second thread of tasks on the plurality of hardware data processing nodes.

公开(公告)号：US20180189102A1

公开(公告)日：2018-07-05

申请号：US15396172

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.

公开(公告)号：US20180081734A1

公开(公告)日：2018-03-22

申请号：US15269957

申请日：2016-09-19

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/52 ,  G06F11/07 ,  G06F9/48

CPC classification number: G06F9/5044 ,  G06F9/4881 ,  G06F9/4887 ,  G06F9/52 ,  G06F9/522 ,  G06F11/0757

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US20180081733A1

公开(公告)日：2018-03-22

申请号：US15269952

申请日：2016-09-19

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/07 ,  G06F9/52

CPC classification number: G06F9/5044 ,  G06F9/4887 ,  G06F9/52 ,  G06F11/0757

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US20170318304A1

公开(公告)日：2017-11-02

申请号：US15653561

申请日：2017-07-19

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Nainala Vyagrheswarudu ,  Vijayavardhan Baireddy ,  Pavan Venkata Shastry

IPC: H04N19/43 ,  H04N19/51

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

公开(公告)号：US20170238003A1

公开(公告)日：2017-08-17

申请号：US15587116

申请日：2017-05-04

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Vipul Paladiya ,  Kapil Ahuja

IPC: H04N19/44 ,  H04N19/423 ,  H04N19/124 ,  H04N19/70 ,  H04N19/625

CPC classification number: H04N19/44 ,  H04N19/124 ,  H04N19/34 ,  H04N19/423 ,  H04N19/625 ,  H04N19/70

Abstract: A progressive JPEG (joint photographic experts group) decoder is disclosed. The progressive JPEG decoder includes a processing unit that receives a plurality of progressive scans and generates a plurality of modified progressive scans (MPSs). A baseline JPEG decoder, coupled to the processing unit, includes a Huffman decoder, an inverse quantization unit and an inverse transform unit. The Huffman decoder receives a current MPS and generates a set of transform coefficients corresponding to the current MPS. The processing unit adds a set of transform coefficients corresponding to a previous MPS to the set of transform coefficients corresponding to the current MPS, and the processing unit generates quantization indices. The inverse quantization unit estimates inverse quantization values based on the quantization indices. The inverse transform unit estimates inverse transform decoded values based on the estimated inverse quantization values and generates a set of pixels corresponding to the current MPS.

公开(公告)号：US09538092B2

公开(公告)日：2017-01-03

申请号：US14599201

申请日：2015-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghavi ,  Rajsekhar Allu

IPC: H04N9/73 ,  H04N5/235 ,  H04N5/355 ,  H04N5/345

CPC classification number: H04N5/2355 ,  H04N5/345 ,  H04N5/35581

Abstract: Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs.

Abstract translation: 公开了产生宽动态范围图像的方法和装置。 示例性装置包括具有第一输入的第一处理块，用于从图像传感器接收输入数据的第二输入和第一输出; 具有第三输入的第二处理块，用于接收来自图像传感器的输入数据的第四输入，以及第二输出，第一和第二输出中的至少一个输出，基于第一，第二，第三和第三输入中的至少两个，输出WDR图像; 第四输入; 具有第五输入和第三输出的架构识别器，用于传送图像传感器的架构类型的第三输出; 功能选择器，具有第四输出，用于基于第三输出来识别第一和第二处理块中的至少一个; 以及传感器适配器，其具有耦合到第四输出的第七输入端，并具有耦合到第一和第三输入端的第五输出端。