公开(公告)号：US20130073754A1

公开(公告)日：2013-03-21

申请号：US13676606

申请日：2012-11-14

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM

IPC: G06F13/00

CPC classification number: G06F13/4291

Abstract: A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.

Abstract translation: 一种方法或设备操作串行互连配置中的多个设备以建立每个设备的设备标识符（ID）。 输入信号通过使用也由第一设备用于输入其它信息（例如，数据，命令，控制信号）的输入通过串行互连传输到第一设备。 发生电路响应于输入信号产生装置ID。 传输电路然后通过第一设备的串行输出将与设备ID相关联的输出信号传送到第二设备。 串行输出也由第一设备用于在串行互连配置中向另一设备输出其他信息（例如，信号，数据）。

公开(公告)号：US20040165608A1

公开(公告)日：2004-08-26

申请号：US10425957

申请日：2003-04-30

Applicant: MOSAID Technologies Incorporated

Inventor： Richard Waterhouse ,  Robert N. McKenzie ,  Lawrence King

IPC: H04L012/56

CPC classification number: G11C15/00

Abstract: A method for reducing the number of cycles required for setting up content addressable memory contexts is disclosed. In particular, the method reduces the number of cycles required for setting up multiple contexts of burst operations, in which each context includes the same data key. Each context includes a special field that is set by the user, called a data reuse field. Setting the data reuse field to a first state indicates that the data from the corresponding context is to be used in the operation. Setting the data reuse field to a second state indicates that the data from the most recent operation is to be used instead. Hence the search data key can be written to a single context, avoiding consumption of cycles required for writing the same search data key to subsequent contexts of the burst operation.

Abstract translation: 公开了一种用于减少设置内容可寻址存储器上下文所需的周期数的方法。 特别地，该方法减少了设置突发操作的多个上下文所需的周期数，其中每个上下文包括相同的数据密钥。 每个上下文包括由用户设置的称为数据重用字段的特殊字段。 将数据重用字段设置为第一状态表示在操作中使用来自相应上下文的数据。 将数据重用字段设置为第二个状态表示将使用来自最近操作的数据。 因此，可以将搜索数据密钥写入单个上下文，避免将用于将相同搜索数据密钥写入到突发操作的后续上下文所需的周期的消耗。

公开(公告)号：US20020075747A1

公开(公告)日：2002-06-20

申请号：US09977088

申请日：2001-10-12

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC: G11C008/00

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract translation: 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置，以及用于接收时钟输入信号并用于传送时钟的抽头延迟线 驱动信号与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

公开(公告)号：US20010046162A1

公开(公告)日：2001-11-29

申请号：US09919752

申请日：2001-07-31

Applicant: MOSAID Technologies Incorporated Kanata

Inventor： Valerie L. Lines

IPC: G11C007/00

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines for application to the enable inputs whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.

公开(公告)号：US20010001601A1

公开(公告)日：2001-05-24

申请号：US09761274

申请日：2001-01-16

Applicant: MOSAID Technologies Incorporated

Inventor： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC: G11C008/00

CPC classification number: G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.