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公开(公告)号：US10546632B2
公开(公告)日：2020-01-28
申请号：US15842496
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20200013463A1
公开(公告)日：2020-01-09
申请号：US16518847
申请日：2019-07-22
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
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公开(公告)号：US10461128B2
公开(公告)日：2019-10-29
申请号：US15497503
申请日：2017-04-26
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Agostino Pirovano , Andrea Redaelli
Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.
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公开(公告)号：US10446226B2
公开(公告)日：2019-10-15
申请号：US15231518
申请日：2016-08-08
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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公开(公告)号：US20190295636A1
公开(公告)日：2019-09-26
申请号：US16436734
申请日：2019-06-10
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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Patent Agency Ranking
公开(公告)号：US10424376B2
公开(公告)日：2019-09-24
申请号：US15853803
申请日：2017-12-24
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano
Abstract: The present disclosure includes apparatuses and methods for material implication operations in memory. An example apparatus may include a plurality of memory cells coupled to a first access line and a plurality of second access lines, and a controller coupled to the plurality of memory cells. The controller of the example apparatus may be configured to apply a first signal to the first access line, and while the first signal is being applied to the first access line, apply a second signal to a first of the plurality of memory cells via another respective one of the plurality of second access lines and apply a third signal to a second of the plurality of memory cells via another respective one of the plurality of second access lines. The material implication operation may be performed as a result of the signals (e.g., first, second, and third signals) applied and a result of the material implication operation is stored on the second of the plurality of memory cells subsequent to the application of the third signal.
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公开(公告)号：US10424374B2
公开(公告)日：2019-09-24
申请号：US15582329
申请日：2017-04-28
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
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公开(公告)号：US10388866B2
公开(公告)日：2019-08-20
申请号：US16184314
申请日：2018-11-08
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto M. Meotto
Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
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公开(公告)号：US20190252606A1
公开(公告)日：2019-08-15
申请号：US15893108
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Kolya Yastrebenetsky , Anna Maria Conti , Fabio Pellizzer
Abstract: Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.
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公开(公告)号：US10374007B2
公开(公告)日：2019-08-06
申请号：US15918770
申请日：2018-03-12
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano
Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
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