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    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS
    9.
    发明申请
    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS 有权
    形成电阻随机访问记忆与保险丝阵列

    公开(公告)号：US20140048763A1

    公开(公告)日：2014-02-20

    申请号：US14066308

    申请日：2013-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Umberto M. Meotto ,  Giorgio Servalli

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L23/5256 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

    Abstract translation: 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。

    MEMORY DEVICES INCLUDING STAIRCASE STRUCTURES
    10.
    发明申请
    MEMORY DEVICES INCLUDING STAIRCASE STRUCTURES 有权

    公开(公告)号：US20250132248A1

    公开(公告)日：2025-04-24

    申请号：US19005952

    申请日：2024-12-30

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Richard J. Hill ,  Umberto M. Meotto ,  Matthew Thorum

    IPC: H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

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