公开(公告)号：US07586996B2

公开(公告)日：2009-09-08

申请号：US11088616

申请日：2005-03-24

Applicant: Patrick Cerisier ,  Patrice Musy

Inventor： Patrick Cerisier ,  Patrice Musy

IPC: H04K1/02 ,  H04B3/46 ,  H04B1/10

CPC classification number: H03G3/3042

Abstract: Filtered digital information representative of the power of an output signal from an amplifier is generated, and control information from a setpoint representative of a desired power for the output signal is generated from the desired response time for the establishment of the power and from a model to be followed for the establishment. In addition, a gain control and a bias current control are established for each initial variable-gain amplifier from the filtered digital information, from the control information and from a polynomial digital regulation of the RST type whose polynomial coefficients are determined from input parameters comprising characteristics of each variable-gain amplifier and from characteristics of the filter generating the filtered digital information.

Abstract translation: 产生代表来自放大器的输出信号的功率的滤波数字信息，并且从用于建立功率的期望响应时间产生来自表示输出信号的期望功率的设定点的控制信息，并且从模型到 随之成立。 另外，对于每个初始可变增益放大器，从经过滤波的数字信息，从控制信息和RST类型的多项式数字调节建立增益控制和偏置电流控制，其多项式系数由包括特性的输入参数确定 并根据滤波器的特性生成滤波后的数字信息。

公开(公告)号：US07457377B2

公开(公告)日：2008-11-25

申请号：US11057600

申请日：2005-02-14

Applicant: Armin Wellig ,  Julien Zory

Inventor： Armin Wellig ,  Julien Zory

IPC: H03D1/00 ,  H03M13/03

CPC classification number: H03M13/451 ,  H03M13/13 ,  H03M13/23 ,  H03M13/3944

Abstract: A system and method is provided for estimating a sequence of N bits ({circumflex over (x)}0{circumflex over (x)}1 . . . {circumflex over (x)}N−1) corresponding to a received sequence of M digital data (r0r1 . . . rM−1). The method includes determining candidate sequences of MRS digital data from a reduced reference sequence space comprising 2NRS reduced reference sequences of MRS reference digital data (s0s1 . . . sMRS−1), MRS being less than M, and 2NRS being less than or equal to 2N. The method further includes making up each candidate sequence with remaining reference symbols to obtain at least one complete candidate sequence of M digital data, and determining the sequence of N bits ({circumflex over (x)}0{circumflex over (x)}1 . . . {circumflex over (x)}N−1) from the complete candidate sequences.

Abstract translation: 提供了一种系统和方法，用于估计与a相对应的N位（x×1×1×1×N-1）的序列 接收到的M个数字数据序列（r 1，...，...，M-1）。 该方法包括从缩减的参考序列空间中确定M SUB数字数据的候选序列，所述缩减的参考序列空间包括2 N 2 参考序列的M RS>>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< SUB2> RS -1，M RS小于M，2 N < SUB2> RS 小于或等于2 N。 该方法还包括用剩余的参考符号组成每个候选序列，以获得M个数字数据的至少一个完整的候选序列，并且确定N个比特的序列（x

公开(公告)号：US20080122676A1

公开(公告)日：2008-05-29

申请号：US11941380

申请日：2007-11-16

Applicant: Friedbert BERENS

Inventor： Friedbert BERENS

IPC: H04L17/02

CPC classification number: H04B1/719 ,  H04B1/71632 ,  H04B1/71635

Abstract: An ultra wide band (UWB) device includes a first control unit for controlling a UWB data stream according to a first operation mode, and a second control unit for controlling the UWB data stream according to a low duty cycle operation mode. An activation unit selectively activates the first and second control units.

Abstract translation: 超宽带（UWB）装置包括用于根据第一操作模式控制UWB数据流的第一控制单元和用于根据低占空比操作模式控制UWB数据流的第二控制单元。 激活单元选择性地激活第一和第二控制单元。

公开(公告)号：US07370246B2

公开(公告)日：2008-05-06

申请号：US11007785

申请日：2004-12-08

Applicant: Armin Wellig ,  Julien Zory

Inventor： Armin Wellig ,  Julien Zory

IPC: H03M13/03 ,  G06F11/00

CPC classification number: H03M13/2778 ,  H03M13/2707 ,  H03M13/276 ,  H04L1/0071

Abstract: Successive sequences of interleaved data samples extracted from a virtual memory having L0 columns and C0 rows are de-interleaved. The de-interleaving includes receiving each sequence of the interleaved data samples, and writing row by row the received sequences of interleaved data samples in a de-interleaving memory array having L rows and C columns, with L being greater or equal to L0 and C being greater or equal to C0. The data samples stored in the de-interleaving memory array are de-interleaved sub-array by sub-array. Each sub-array is a square cluster array having a number SQ of rows and columns. A cluster array is a row of the square cluster array comprising SQ data samples, with the number L of rows and the number C of columns of the de-interleaving memory array being multiples of the number SQ of rows and columns.

Abstract translation: 从具有L0列和C0行的虚拟存储器提取的交错数据样本的连续序列被解交织。 解交织包括接收交织的数据样本的每个序列，并且将所接收的交错数据样本序列逐行地写入具有L行和C列的解交织存储器阵列中，其中L大于或等于L0和C 大于或等于C0。 存储在解交织存储器阵列中的数据样本是通过子阵列去交织的子阵列。 每个子阵列是具有数字SQ行和列的方阵集阵列。 集群阵列是包括SQ数据样本的平方簇阵列，其行数为L，解交织存储器阵列的列的数目C为行和列的数量SQ的倍数。

公开(公告)号：US07321608B2

公开(公告)日：2008-01-22

申请号：US10794768

申请日：2004-03-05

Applicant: Lydi Smaini ,  Didier Helal

Inventor： Lydi Smaini ,  Didier Helal

IPC: H04B1/00

CPC classification number: H04B1/7174 ,  H04L25/4902

Abstract: Successive groups of N bits are delivered at a delivery frequency Fe greater than a predetermined frequency PRF. At least one of the successive groups includes at least one subgroup of at least one bit defining at least one digital cue of position and of shape of at least one base pulse within a window of length 1/PRF. This digital cue is converted into the base pulse, and the base pulse is filtered using a high-pass filter for providing a pulse of the ultra wideband type within the window with a temporal accuracy equal to 1/N*Fe.

Abstract translation: N个比特的连续组以大于预定频率PRF的传送频率Fe传送。 连续组中的至少一个包括至少一个位的至少一个子群，其限定长度为1 / PRF的窗口内的至少一个基本脉冲的位置和形状的至少一个数字提示。 该数字提示被转换成基本脉冲，并且使用高通滤波器对基本脉冲进行滤波，以便以等于1 / N * Fe的时间精度在窗口内提供超宽带类型的脉冲。

公开(公告)号：US20080016317A1

公开(公告)日：2008-01-17

申请号：US11768462

申请日：2007-06-26

Applicant: Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

Inventor： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

IPC: G06F15/00

CPC classification number: G06F12/084 ,  G06F12/0886 ,  Y02D10/13

Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Abstract translation: 耦合到包括处理器集群的处理器的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供用于存储用于处理的数据的数据位置同时操作标量和矢量数据。 数据位置以标量模式或矢量模式进行访问。 这通过明确地映射标量的数据位置和矢量的数据位置来完成。

公开(公告)号：US20070297523A1

公开(公告)日：2007-12-27

申请号：US11686545

申请日：2007-03-15

Applicant: Chiara Cattaneo ,  Philippe Rouzet ,  Regis Cattenoz ,  Patrick Conti

Inventor： Chiara Cattaneo ,  Philippe Rouzet ,  Regis Cattenoz ,  Patrick Conti

IPC: H04L23/02

CPC classification number: H04L27/2626 ,  H04L27/368

Abstract: A calibration is performed tone per tone during interframe spacing. A peak detection is used for measuring the level of the corresponding signal, and a gain correction coefficient is stored for correcting the digital complex modulation coefficients provided by the mapping.

Abstract translation: 在帧间间隔期间，每个音调执行校准。 使用峰值检测来测量相应信号的电平，并且存储增益校正系数以校正由映射提供的数字复调制系数。

公开(公告)号：US07239687B1

公开(公告)日：2007-07-03

申请号：US09582637

申请日：1999-01-28

Applicant: Sven-Rune Olofsson ,  Lennart Olsson ,  Joachim Johansson ,  Hans Ohman ,  Mikael Isaksson ,  Magnus Johansson ,  Tomas Stefansson ,  Gunnar Bahlenberg ,  Anders Isaksson ,  Goran Okvist ,  Lis-Marie Ljunggren ,  Daniel Bengtsson

Inventor： Sven-Rune Olofsson ,  Lennart Olsson ,  Joachim Johansson ,  Hans Ohman ,  Mikael Isaksson ,  Magnus Johansson ,  Tomas Stefansson ,  Gunnar Bahlenberg ,  Anders Isaksson ,  Goran Okvist ,  Lis-Marie Ljunggren ,  Daniel Bengtsson

IPC: H04M1/24 ,  H04M3/08 ,  H04M3/22

CPC classification number: H04M11/062

Abstract: When delivering a broadband service, such as xDSL, without inband POTS, it is necessary to separate the analogue POTS signal and the xDSL signal from each other at both the CO (Central Office) and the CP (Customer's Premises). This can be achieved by using an active POTS splitter. The present invention incorporates test functionality for the line between the CP and the CO, or ONU (Optical Network Unit), in the POTS splitter. This enables two-sided measurements on the line, both during installation and during operation. The measurements are performed at the CO and upon request, or when the test device automatically sends a test message/signal. In this way there is no need for field technicians at the CP side. The POTS splitter can have a unique identity code that is transmitted to the CO each time a test is started, or on receipt of a request from the CO.

Abstract translation: 在提供无带宽POTS等宽带业务（如xDSL）的情况下，有必要在CO（中心局）和CP（客户的场所）上分开模拟POTS信号和xDSL信号。 这可以通过使用活动的POTS分离器来实现。 本发明包括在POTS分离器之间的CP和CO之间的线路的测试功能，或ONU（光网络单元）。 这可以在安装和运行期间在线进行双面测量。 测量在CO和根据请求执行，或当测试设备自动发送测试消息/信号时执行。 这样就不需要在CP方面的​​现场技术人员。 POTS分离器可以具有唯一的身份码，每当测试开始时，或者在接收到来自CO的请求时，它被传送到CO。

公开(公告)号：US07177605B2

公开(公告)日：2007-02-13

申请号：US10754465

申请日：2004-01-09

Applicant: Patrick Cerisier ,  Giovanni Cerusa

Inventor： Patrick Cerisier ,  Giovanni Cerusa

IPC: H04B1/04 ,  H01Q11/12

CPC classification number: H03F3/211 ,  H03F3/2175 ,  H03F2200/331 ,  H03F2200/372

Abstract: A power amplification device includes an input for receiving a signal having a useful or desired frequency band, and power amplification circuitry of the delta-sigma type connected to the input. The power amplification circuitry exhibits an order greater than or equal to one in the useful frequency band, and an order greater than or equal to one outside the useful frequency band.

Abstract translation: 功率放大装置包括用于接收具有有用或期望频带的信号的输入端和连接到输入端的Δ-Σ型功率放大电路。 功率放大电路在有用频带中呈现大于或等于1的阶数，以及在有用频带外的大于或等于1的阶数。

公开(公告)号：US20060156163A1

公开(公告)日：2006-07-13

申请号：US11293460

申请日：2005-12-02

Applicant: Friedbert Berens ,  Laurent Chalard ,  Stephane Tanrikulu ,  Ettore Messina

Inventor： Friedbert Berens ,  Laurent Chalard ,  Stephane Tanrikulu ,  Ettore Messina

IPC: H04L1/18 ,  G08C25/02

CPC classification number: H04L1/1845 ,  H04L1/005 ,  H04L1/0055 ,  H04L1/0057 ,  H04L1/0066 ,  H04L1/1816 ,  H04L1/1819

Abstract: A device for decoding an incident FEC encoded packet of data within an ARQ scheme. The device includes a processor or processing means for performing successive decoding processes of successive intermediate FEC code encoded packets related to the incident FEC code encoded packet. The processor or processing means includes a FEC decoder. The processor or processing means included a determination unit or determination means for determining initial decoding conditions from the FEC code decoding result concerning the preceding intermediate FEC code encoded packet and from the current intermediate FEC code encoded packet, and the FEC decoder is for performing the current FEC code decoding using the initial decoding conditions.

Abstract translation: 一种用于解码ARQ方案内的数据的入局FEC编码分组的装置。 该装置包括处理器或处理装置，用于执行与入射的FEC码编码包有关的连续中间FEC码编码包的连续解码处理。 处理器或处理装置包括FEC解码器。 处理器或处理装置包括确定单元或确定装置，用于根据关于前述中间FEC编码分组的FEC码解码结果和当前中间FEC编码分组确定初始解码条件，并且FEC解码器用于执行当前 FEC码解码使用初始解码条件。