-
公开(公告)号：US11925013B2
公开(公告)日：2024-03-05
申请号：US17735414
申请日：2022-05-03
发明人： Nozomu Harada , Koji Sakui
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096 , G11C11/412
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096 , G11C11/412
摘要： Si pillars 22a to 22d stand on an N+ layer 21 connected to a source line SL. Lower portions of the Si pillars 22a to 22d are surrounded by a HfO2 layer 25a, which is surrounded by TiN layers 26a and 26b that are respectively connected to plate lines PL1 and PL2 and are isolated from each other. Upper portions of the Si pillars 22a to 22d are surrounded by a HfO2 layer 25b, which is surrounded by TiN layers 28a and 28b that are respectively connected to word lines WL1 and WL2 and are isolated from each other. A thickness Lg1 of the TiN layer 26a on a line X-X′ is smaller than twice a thickness Lg2 of the TiN layer 26a on a line Y-Y′ and is larger than or equal to the thickness Lg2. The thickness Lg1 of the TiN layer 28a on the line X-X′ is smaller than twice the thickness Lg2 of the TiN layer 28a on the line Y-Y′.
-
公开(公告)号：US11915757B2
公开(公告)日：2024-02-27
申请号：US17741975
申请日：2022-05-11
发明人： Koji Sakui , Nozomu Harada
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/16
摘要： A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form, and controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer of each of the memory cells included in the pages to perform a page write operation of holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, and the second impurity layer to perform a page erase operation of removing the hole group out of the channel semiconductor layer.
-
公开(公告)号：US20230410893A1
公开(公告)日：2023-12-21
申请号：US18229049
申请日：2023-08-01
发明人： Koji SAKUI , Nozomu Harada
IPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4094
CPC分类号： G11C11/4096 , G11C11/4094 , G11C11/4091
摘要： A semiconductor element memory device includes a first block including first memory cells arranged in a matrix, and/or a second block including second memory cells each formed of two memory cells. The memory device is configured to perform a data hold operation of controlling voltages to be applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines to hold, in a semiconductor base, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate lines, the word lines, the source line, the odd-numbered bit lines, and the even-numbered bit lines to discharge the positive hole group from the semiconductor base. The number of first blocks and the number of second blocks are variable in the memory device that is in operation.
-
公开(公告)号：US20230397397A1
公开(公告)日：2023-12-07
申请号：US18450767
申请日：2023-08-16
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/4096 , G11C11/404
摘要： A memory device according to the present invention includes memory cells each of which is formed of a semiconductor body that stands on a substrate in a vertical direction relative to the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of the memory cell are controlled to perform a write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform an erase operation of discharging the group of positive holes from inside the semiconductor body. The first impurity region of the memory cell is connected to a source line wiring layer, the second impurity region thereof is connected to a bit line wiring layer, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line wiring layer, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line wiring layer, and in the vertical direction relative to the substrate, the source line wiring layer is connected to the first impurity region at a position lower than the first driving control line wiring layer and the word line wiring layer.
-
公开(公告)号：US20230377635A1
公开(公告)日：2023-11-23
申请号：US18228433
申请日：2023-07-31
发明人： Koji SAKUI , Nozomu Harada
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4094 , G11C11/4091
CPC分类号： G11C11/4096 , G11C11/4085 , G11C11/4094 , G11C11/4091
摘要： A memory device uses semiconductor elements. By controlling voltages applied to plate lines, word lines, source lines, and bit lines, the memory device performs a data write operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a data erase operation of removing positive hole groups from inside the semiconductor base material. The memory device includes a block made up of memory cells, which are arrayed in a matrix. Storage data of memory cells connected with a first word line, i.e., a selected one of the word lines, in the block is read to the bit lines by applying a first voltage to the first word line, and a second voltage to a second word line adjacent to the first word line.
-
公开(公告)号：US11823727B2
公开(公告)日：2023-11-21
申请号：US17719646
申请日：2022-04-13
发明人： Koji Sakui , Nozomu Harada
IPC分类号： G11C11/34 , G11C11/404 , G11C11/4096 , G11C11/4091 , G11C11/406 , H10B12/00
CPC分类号： G11C11/404 , G11C11/406 , G11C11/4091 , G11C11/4096 , H10B12/20
摘要： A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, the first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line, the bit line is connected to a sense amplifier circuit with a first switch circuit therebetween, and in a page refresh operation, page data in a first group of memory cells belonging to a first page is read to the sense amplifier circuits, the first switch circuit is put in a non-conducting state, the page erase operation of the first group of memory cells is performed, the first switch circuit is put in a conducting state, and the page write operation of writing the page data in the sense amplifier circuits back to the first group of memory cells is performed.
-
公开(公告)号：US11823726B2
公开(公告)日：2023-11-21
申请号：US17719628
申请日：2022-04-13
发明人： Koji Sakui , Nozomu Harada
IPC分类号： G11C11/24 , G11C11/402 , G11C11/4097
CPC分类号： G11C11/4023 , G11C11/4097
摘要： A memory device includes a plurality of pages arranged in columns, each page is constituted by a plurality of memory cells arranged in rows on a substrate, the memory cells included in the page are memory cells of a plurality of semiconductor base materials that stand on the substrate in a vertical direction or that extend in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, and all memory cells included in a first page subjected to the page erase operation perform the page write operation at least once.
-
公开(公告)号：US20230335183A1
公开(公告)日：2023-10-19
申请号：US18299363
申请日：2023-04-12
发明人： Koji Sakui , Nozomu Harada
IPC分类号： G11C11/4097 , H10B12/00 , G11C11/4091 , G11C11/4096
CPC分类号： G11C11/4097 , H10B12/20 , G11C11/4091 , G11C11/4096
摘要： A memory device includes pages including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes. The first and second impurity regions and first and second gate conductor layers are connected to source, bit, plate, and word lines. In a page write operation, a channel semiconductor layer is at a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the channel semiconductor layer is at a second data retention voltage, a positive voltage pulse is applied to at least one of the word and plate lines of a selected page, and a ground voltage is applied to the word and plate lines of a non-selected page and to all of the source and bit lines.
-
公开(公告)号：US20230327001A1
公开(公告)日：2023-10-12
申请号：US18319716
申请日：2023-05-18
发明人： Nozomu HARADA , Kenichi KANAZAWA
IPC分类号： H01L29/423 , H10B10/00 , H01L29/66
CPC分类号： H01L29/66666 , H01L29/42392 , H10B10/12
摘要： P+ layers which entirely cover top parts of Si pillars and which surround the Si pillars at equal widths in a plan view are formed by self-alignment with the Si pillars, W layers are formed on the P+ layers, a band-shaped contact hole which is in contact with respective partial regions of the W layers and which extends in the Y direction is formed, and a supply wiring metal layer is formed by filling the band-shaped contact hole. The partial regions of the W layers are shaped so as to protrude to outside of the band-shaped contact hole in a plan view.
-
公开(公告)号：US11776609B2
公开(公告)日：2023-10-03
申请号：US17717808
申请日：2022-04-11
发明人： Nozomu Harada , Koji Sakui
IPC分类号： G11C11/402 , G11C11/409
CPC分类号： G11C11/4023 , G11C11/409
摘要： In a dynamic flash memory cell including: a HfO2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate; a HfO2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N+ layers connected to a bottom portion and a top portion of the Si pillar, and an SGT transistor including: a SiO2 layer surrounding a lower portion of a Si pillar standing on the same P-layer substrate; a HfO2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N+ layers sandwiching the HfO2 layer in a perpendicular direction and connected to a top portion and a middle portion of the Si pillar, bottom positions of the Si pillar and the Si pillar are at the same position A. A bottom portion of an upper transistor portion of the dynamic flash memory cell composed of the HfO2 layer and the TiN layer in an upper portion of the Si pillar, and a bottom portion of an SGT transistor portion composed of the HfO2 layer and the TiN layer in an upper portion of the Si pillar are at the same position B.
-
-
-
-
-
-
-
-
-
搜索结果
543 条记录 (耗时 0.034 秒)
