公开(公告)号：US10937868B2

公开(公告)日：2021-03-02

申请号：US16513832

申请日：2019-07-17

申请人： ATOMERA INCORPORATED

发明人： Richard Burton ,  Marek Hytha ,  Robert J. Mears

IPC分类号： H01L29/16 ,  H01L29/15 ,  H01L29/80 ,  H01L29/66 ,  H01L29/93 ,  H01L29/78

摘要： A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.

公开(公告)号：US20210020749A1

公开(公告)日：2021-01-21

申请号：US16513825

申请日：2019-07-17

申请人： ATOMERA INCORPORATED

发明人： Richard Burton ,  Marek Hytha ,  Robert J. Mears

IPC分类号： H01L29/15 ,  H01L29/16 ,  H01L29/80 ,  H01L29/78 ,  H01L29/93 ,  H01L29/66

摘要： A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt region may include a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The semiconductor device may further include a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.

公开(公告)号：US10884185B2

公开(公告)日：2021-01-05

申请号：US16380111

申请日：2019-04-10

申请人： ATOMERA INCORPORATED

发明人： Robert John Stephenson

IPC分类号： H01L33/06 ,  H01L23/522 ,  H01L27/15 ,  G02B6/12 ,  H01L27/12 ,  H01L29/15 ,  G02B6/134 ,  H01L33/00 ,  H01L33/34 ,  H01L33/58

摘要： A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include an active device layer on the superlattice including at least one active semiconductor device.

公开(公告)号：US20200343380A1

公开(公告)日：2020-10-29

申请号：US16853875

申请日：2020-04-21

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  Richard Burton ,  Yung-Hsuan Yang

IPC分类号： H01L29/78 ,  H01L29/15 ,  H01L29/06 ,  H01L29/10

摘要： A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

公开(公告)号：US10763370B2

公开(公告)日：2020-09-01

申请号：US16380149

申请日：2019-04-10

申请人： ATOMERA INCORPORATED

发明人： Robert John Stephenson

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06 ,  H01L29/15 ,  H01L29/66

摘要： A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.

公开(公告)号：US20200161430A1

公开(公告)日：2020-05-21

申请号：US16193011

申请日：2018-11-16

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  Daniel Connelly ,  Marek Hytha ,  Richard Burton ,  Robert J. Mears

IPC分类号： H01L29/15 ,  H01L27/088

摘要： A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：US10529768B2

公开(公告)日：2020-01-07

申请号：US15843113

申请日：2017-12-15

申请人： ATOMERA INCORPORATED

发明人： Yi-Ann Chen ,  Abid Husain ,  Hideki Takeuchi

IPC分类号： H01L27/146 ,  H01L29/15 ,  H01L29/10 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

摘要： A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.

公开(公告)号：US20190319136A1

公开(公告)日：2019-10-17

申请号：US16380149

申请日：2019-04-10

申请人： ATOMERA INCORPORATED

发明人： Robert John Stephenson

IPC分类号： H01L29/786 ,  H01L29/15 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

摘要： A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include source and drain regions on opposing ends of the inverted T channel, and a gate overlying the inverted T channel between the source and drain regions.

公开(公告)号：US20190319135A1

公开(公告)日：2019-10-17

申请号：US16380142

申请日：2019-04-10

申请人： ATOMERA INCORPORATED

发明人： ROBERT JOHN STEPHENSON

IPC分类号： H01L29/786 ,  H01L29/15 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

摘要： A method for making a semiconductor device may include forming an inverted T channel on a substrate, with the inverted T channel comprising a superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions on opposing ends of the inverted T channel, and forming a gate overlying the inverted T channel between the source and drain.

公开(公告)号：US10396223B2

公开(公告)日：2019-08-27

申请号：US15843044

申请日：2017-12-15

申请人： ATOMERA INCORPORATED

发明人： Yi-Ann Chen ,  Abid Husain ,  Hideki Takeuchi

IPC分类号： H01L27/00 ,  H01L31/00 ,  H01L31/0352 ,  H01L27/146 ,  H01L31/18 ,  H01L31/109

摘要： A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.