公开(公告)号：US20090086751A1

公开(公告)日：2009-04-02

申请号：US11863192

申请日：2007-09-27

申请人： Chi-Lie Wang ,  Jason Z. Mo ,  Bertan Tezcan

发明人： Chi-Lie Wang ,  Jason Z. Mo ,  Bertan Tezcan

IPC分类号： H04L12/56

CPC分类号： H04L47/28 ,  H04L47/30 ,  H04L47/33 ,  H04L49/90

摘要： A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.

摘要翻译： 串行缓冲器被配置为通过数据分组传送路径将多个接收到的数据分组发送到主机处理器。 串行缓冲器的门铃控制器通过数据包传送路径监视发送到主机处理器的数据包的数量，并估计主机处理器实际接收到的数据包的数量。 门铃控制器每当估计的数据分组数与帧中的固定数量的数据分组对应时，就产生门铃命令。 门铃命令在门铃命令路径上传送到主机处理器，该命令路径比数据包传送路径快。 门铃控制器可以响应于第一延迟值估计主处理器实际接收的数据分组的数量，其表示门铃命令路径比数据分组传送路径多得多的速度。

公开(公告)号：US20080209084A1

公开(公告)日：2008-08-28

申请号：US11679820

申请日：2007-02-27

申请人： Chi-Lie Wang ,  Bertan Tezcan

发明人： Chi-Lie Wang ,  Bertan Tezcan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

摘要翻译： 串行缓冲器包括配置为存储从主机接收的数据包的队列。 直接存储器访问（DMA）引擎从具有达到相应水印的水位的最高优先级队列接收数据分组。 DMA引擎被配置为响应于从多个DMA寄存器组中选择的DMA寄存器集合。 用于配置DMA引擎的DMA寄存器组可以响应于读取的数据分组的头部中的信息，或响应于读取数据分组的队列而被选择。 每个DMA寄存器集定义系统存储器中相应的缓冲区，数据包被传输到该缓冲区。 每个DMA寄存器集还定义相应的缓冲器是否以卷绕模式或停止模式被访问，以及是否响应于传送到相应缓冲器中的最后地址而生成门铃信号。

公开(公告)号：US20060248376A1

公开(公告)日：2006-11-02

申请号：US11395570

申请日：2006-03-31

申请人： Bertan Tezcan ,  William Beane ,  Scott Darnell

发明人： Bertan Tezcan ,  William Beane ,  Scott Darnell

IPC分类号： G06F11/00

CPC分类号： H04L49/30 ,  H04L45/52 ,  H04L47/70 ,  H04L49/10 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/3063 ,  H04L49/35

摘要： A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

摘要翻译： 分组处理集成电路芯片包括被配置为从相应的外部源接收分组的多个输入端口和被配置为向相应的外部接收者发送分组的多个输出端口。 芯片还包括可配置为从接收到的分组的有效载荷中提取数据的分组处理器，以处理所提取的数据以产生具有与外部接收者的数据结构兼容的格式的有效载荷的新分组，并将新分组传送到输出端口 。 芯片还可以包括分组交换结构，其被配置为将选择的分组从输入端口路由到选择的输出端口，而无需净荷修改。

公开(公告)号：US06972978B1

公开(公告)日：2005-12-06

申请号：US10663860

申请日：2003-09-16

申请人： Michael Miller ,  Bertan Tezcan ,  Kee Park ,  Scott Yu-Fan Chu

发明人： Michael Miller ,  Bertan Tezcan ,  Kee Park ,  Scott Yu-Fan Chu

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： A CAM array block is configured to perform a search operation in a staged segment-to-segment manner using a plurality of hybrid comparands that are pipelined into the CAM array block during consecutive stages of the search operation. These hybrid comparands include at least a virtual sector field and a data field. The CAM array block is also responsive to a segment address, which identifies an active segment of CAM cells in said CAM array block. The CAM array block may include a CAM array and a global mask cell sub-array that is electrically coupled to the CAM array. This global mask cell sub-array may be responsive to the segment address and a mode select signal. A bit/data line control circuit is also provided. The bit/data line control circuit is electrically coupled to the CAM array by bit lines and data lines and has inputs that are responsive to signals generated by the global mask cell sub-array. The device may also include an address translation unit that is responsive to an input address. This address translation unit may be a RAM device that receives a second portion of an input address as a read address. The RAM device may generate at least the virtual sector field and the segment address.

摘要翻译： CAM阵列块被配置为使用在搜索操作的连续阶段期间被流水线化到CAM阵列块中的多个混合对比来以分段的段到段的方式执行搜索操作。 这些混合比较包括至少虚拟扇区字段和数据字段。 CAM阵列块还响应于段地址，其标识所述CAM阵列块中的CAM单元的活动段。 CAM阵列块可以包括CAM阵列和电耦合到CAM阵列的全局掩模单元子阵列。 该全局掩模单元子阵列可以响应于段地址和模式选择信号。 还提供了位/数据线控制电路。 位/数据线控制电路通过位线和数据线电耦合到CAM阵列，并且具有响应于由全局掩模单元子阵列产生的信号的输入。 该设备还可以包括响应于输入地址的地址转换单元。 该地址转换单元可以是接收作为读取地址的输入地址的第二部分的RAM设备。 RAM设备可以至少生成虚拟扇区字段和段地址。

公开(公告)号：US06304196B1

公开(公告)日：2001-10-16

申请号：US09692602

申请日：2000-10-19

申请人： Greg Copeland ,  Bertan Tezcan

发明人： Greg Copeland ,  Bertan Tezcan

IPC分类号： H03M700

CPC分类号： H04N19/60

摘要： A system and method for encoding and decoding data utilizes Walsh-Hadamard Transforms and inversion techniques to generate the possible minimum disparity values for the data to be encoded. A minimum disparity value is then selected that also provides sufficient transition density.

摘要翻译： 用于编码和解码数据的系统和方法利用沃尔什 - 哈达玛变换和反演技术来产生要被编码的数据的可能的最小视差值。 然后选择也提供足够的转变密度的最小视差值。