公开(公告)号：US06554195B1

公开(公告)日：2003-04-29

申请号：US09422020

申请日：1999-10-20

Applicant: Nai-Shung Chang ,  Lie-Wen Chen ,  Ching-Fu Chuang ,  Chia-Hsing Yu

Inventor： Nai-Shung Chang ,  Lie-Wen Chen ,  Ching-Fu Chuang ,  Chia-Hsing Yu

IPC: G06K1906

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  H05K1/023 ,  H05K1/0262 ,  H05K1/117 ,  H05K1/141 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/10022 ,  H05K2201/10196 ,  H05K2201/10325 ,  H05K2201/10689

Abstract: A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.

Abstract translation: 一种双处理器适配器卡，其具有多个电引脚，用于插入到主板上的处理器插槽中，通过该处理器插槽将适配器卡电耦合到主板。 适配器卡上有一个第一和第二个处理器插座，分别用于承载第一和第二处理器。 第一和第二处理器插座各自具有多个对应的引脚，第一和第二处理器插座的一部分引脚对应于电引脚的一部分。 相应的引脚耦合在一起。 此外，在第一和第二处理器插座中用作端子引线的每个引脚连接到上拉电阻器，并且上拉电阻器连接到端子电压。 此外，用于将时钟脉冲信号同步的零延迟缓冲器和用于将电源电压调节到合适工作电压的电压调节器分别安装在适配器卡上并分别耦合到第一和第二处理器插槽。

公开(公告)号：US06384346B1

公开(公告)日：2002-05-07

申请号：US09688037

申请日：2000-10-12

Applicant: Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

Inventor： Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

IPC: H01R909

CPC classification number: H05K7/1459 ,  H05K1/0216 ,  H05K2201/044 ,  H05K2201/09236

Abstract: A trace layout of a printed circuit board (PCB) is provided with a north bridge, at least a peripheral component interconnect (PCI) slot, and an accelerate graphics port (AGP) slot. The PCB includes at least a first trace layer and a second trace layer under the first trace layer. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces, and a number of second traces. The first traces are used for connecting the north bridge to the PCI slot while the second traces are used to connect the north bridge to the AGP slot. Some of the first traces are on the second trace layer under the AGP slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer and the other of the second traces are on the second trace layer.

Abstract translation: 印刷电路板（PCB）的迹线布局提供有北桥，至少外围组件互连（PCI）插槽和加速图形端口（AGP）插槽。 PCB包括至少第一迹线层和第一迹线层下的第二迹线层。 AGP插槽安装在北桥和PCI插槽之间。 PCB还包括多个第一迹线和多个第二迹线。 第一条迹线用于将北桥连接到PCI插槽，而第二条路径用于将北桥连接到AGP插槽。 一些第一个迹线位于AGP插槽下的第二个跟踪层上，而第一个迹线中的另一个迹线位于第一个跟踪层或第二个跟踪层上，并跟踪AGP插槽。 大多数第二迹线位于第一迹线层上，而第二迹线中的另一条迹线位于第二迹线层上。

公开(公告)号：US6084425A

公开(公告)日：2000-07-04

申请号：US96057

申请日：1998-06-11

Applicant: Yuantsang Liaw ,  Ching-Fu Chuang ,  Nai-Shung Chang

Inventor： Yuantsang Liaw ,  Ching-Fu Chuang ,  Nai-Shung Chang

IPC: H03H7/40 ,  G01R19/00

CPC classification number: H03H7/40

Abstract: An impedance adjusting apparatus of a controlling chip on a computer mainboard. When a computer is turned on, BIOS automatically detects the actual usage of the memory sockets, and then sends corresponding control signals to adjust the impedance of the impedance adjusting apparatus for a better impedance matching between the controlling chip and the memory sockets. The signal reflection is dramatically reduced and the operation bandwidth is widened.

Abstract translation: 一种在计算机主板上的控制芯片的阻抗调节装置。 当计算机打开时，BIOS会自动检测内存插槽的实际使用情况，然后发送相应的控制信号，调整阻抗调整装置的阻抗，以便控制芯片和存储器插槽之间更好的阻抗匹配。 信号反射明显减少，工作带宽扩大。

公开(公告)号：US20140308947A1

公开(公告)日：2014-10-16

申请号：US13986215

申请日：2013-04-15

Applicant: Ching-Fu Chuang

Inventor： Ching-Fu Chuang

IPC: H04W4/22

CPC classification number: H04W4/90 ,  G01S13/56 ,  G08B13/2491

Abstract: The invention relates to a theft-prevention system for a mobile phone, primarily comprising a detection control system and a mobile phone, wherein the detection control system includes a microwave emitter, detection unit, and alarm tone, and a microwave reception unit is fit within the mobile phone, with said microwave reception unit being integrated into the mobile phone system; as a result, when the detection control system senses that someone is approaching or breaking in, it will emit a microwave signal to the microwave reception unit, while at the same time emitting an alarm tone, as well as activating the speaker of the mobile phone to notify the user indicates that someone has come within the set range, allowing the owner of the mobile phone to immediately act in response. The invention thus provides a more user-friendly, mobile phone-integrated theft-prevention system.

Abstract translation: 本发明涉及一种主要包括检测控制系统和移动电话的移动电话防盗系统，其中检测控制系统包括微波发射器，检测单元和报警音，微波接收单元适合于 所述移动电话将所述微波接收单元集成到所述移动电话系统中; 结果，当检测控制系统感测到某人正在接近或断开时，它将向微波接收单元发出微波信号，同时发出报警音，以及启动移动电话的扬声器 通知用户指示有人已经进入设定范围，允许手机的所有者立即作出响应。 因此，本发明提供了一种更加用户友好的移动电话集成的防盗系统。