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公开(公告)号：US08316378B2
公开(公告)日：2012-11-20
申请号：US12254201
申请日：2008-10-20
Applicant: John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
Inventor： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
CPC classification number: H04B1/71055 , H04B1/7105 , H04B2201/70711 , H04J13/0077
Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
Abstract translation: 一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。 该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。 该方法还包括处理第二数据处理模块中的至少一个信号时隙的数据，以及在完成对第二数据处理模块中的至少一个数据块的处理的完成时启用第三数据处理模块，并且确定 第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。
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公开(公告)号：US20080080542A1
公开(公告)日：2008-04-03
申请号：US11529148
申请日：2006-09-28
Applicant: Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
Inventor： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
IPC: H04L12/56
CPC classification number: H04B1/707 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0067
Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
Abstract translation: 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器， 以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。 后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收 解码的传输信道位。
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公开(公告)号：US09342479B2
公开(公告)日：2016-05-17
申请号：US13592617
申请日：2012-08-23
Applicant: Jose Fridman , Ajay Anant Ingle , Deepak Mathew , Marc M. Hoffman , Michael John Lopez
Inventor： Jose Fridman , Ajay Anant Ingle , Deepak Mathew , Marc M. Hoffman , Michael John Lopez
CPC classification number: G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109
Abstract: Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
Abstract translation: 公开了一种向量处理器中数据提取的系统和方法。 在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。 该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的地寄存器复制到存储器。
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公开(公告)号：US08054922B2
公开(公告)日：2011-11-08
申请号：US12189529
申请日：2008-08-11
Applicant: Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
Inventor： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
IPC: H04B1/10
CPC classification number: H04L27/34 , H04L27/3809
Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.
Abstract translation: 系统包括用于接收调制信号的接收机。 接收机包括用于将表示调制信号的星座点的复数数据转换为标量数据表示的增益估计器。 增益估计器被配置为将标量数据表示的第一部分折叠到标量数据表示的第二部分上。 增益估计器还被配置为从标量数据表示的折叠的第一部分和第二部分估计星座增益值。
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公开(公告)号：US20090165019A1
公开(公告)日：2009-06-25
申请号：US12254201
申请日：2008-10-20
Applicant: John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
Inventor： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
IPC: G06F9/46
CPC classification number: H04B1/71055 , H04B1/7105 , H04B2201/70711 , H04J13/0077
Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
Abstract translation: 一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。 该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。 该方法还包括处理第二数据处理模块中的至少一个信号时隙的数据，以及在完成对第二数据处理模块中的至少一个数据块的处理的完成时启用第三数据处理模块，并且确定 第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。
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Patent Agency Ranking
公开(公告)号：US20090081973A1
公开(公告)日：2009-03-26
申请号：US11904109
申请日：2007-09-26
Applicant: Aiguo Yan , Jonathan Richard Strange , Bernard Mark Tenbroek , Deepak Mathew , Liang Ma
Inventor： Aiguo Yan , Jonathan Richard Strange , Bernard Mark Tenbroek , Deepak Mathew , Liang Ma
IPC: H04B1/04
CPC classification number: H04W52/52 , H04W52/04 , H04W52/14 , H04W52/146
Abstract: Methods and apparatus are provided for controlling transmitted power in a wireless system. The method includes generating information to be transmitted as a series of signal bursts, with a time interval between successive signal bursts, controlling individually a power level of each of said signal bursts with a power control signal to provide output signal bursts to be transmitted, and asserting a new power value of the power control signal during the time interval preceding each signal burst. The wireless system can be a TDSCDMA wireless system, and the signal bursts can be uplink signal bursts.
Abstract translation: 提供了用于控制无线系统中的发射功率的方法和装置。 该方法包括产生要作为一系列信号突发发送的信息，具有连续的信号脉冲串之间的时间间隔，用功率控制信号单独地控制每个所述信号脉冲串的功率电平以提供要传输的输出信号脉冲串;以及 在每个信号突发之前的时间间隔内断言功率控制信号的新功率值。 无线系统可以是TDSCDMA无线系统，信号突发可以是上行链路信号突发。
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公开(公告)号：US08149702B2
公开(公告)日：2012-04-03
申请号：US12199640
申请日：2008-08-27
Applicant: Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
Inventor： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
IPC: H04J1/16
CPC classification number: G06F15/7842 , H04L1/0045 , H04L1/0052 , H04L1/1829
Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
Abstract translation: 一种用于在无线系统中处理信号的装置包括用于从一组物理信道接收输入数据的第一存储器模块，用于处理输入数据的第一多个子模块。 第一多个子模块中的每一个被选择为基于数据和传输信道规范起作用。 该装置还包括用于接收经处理的输入数据和输出中间数据的第二存储器模块。 第二存储器中的输入数据的位置与数据和传输通道规范相关联地被分配。 该装置还包括用于处理中间数据的第二多个子模块。 第二多个子模块中的每一个被选择为基于数据和传输信道规范起作用。 该装置还包括用于接收和输出比特率处理输出的第三存储器模块。
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公开(公告)号：US08094641B2
公开(公告)日：2012-01-10
申请号：US12194516
申请日：2008-08-19
Applicant: Deepak Mathew , Russ Mestechkin , Prahallada Ponnathota , Thomas F. Howe , Timothy Perrin Fisher-Jeffes
Inventor： Deepak Mathew , Russ Mestechkin , Prahallada Ponnathota , Thomas F. Howe , Timothy Perrin Fisher-Jeffes
IPC: H04B7/216
CPC classification number: H04B1/707 , G06F5/16 , G11C7/1075 , H04B2201/70707
Abstract: A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.
Abstract translation: 无线设备具有BRP-CRP接口，其包括具有第一接入端口和第二接入端口的双端口帧存储器，其中可以通过第一接入端口将数据写入双端口帧存储器，同时该 通过第二个访问端口从双端口帧存储器中读取数据。 比特率处理器对输入数据执行比特率处理，并将通过比特率处理产生的数据通过第一接入端口写入双端口帧存储器。 芯片速率处理器通过第二访问端口从双端口帧存储器读取数据，并对从双端口帧存储器读取的数据执行码片速率处理。 数据处理器执行通过第一访问端口向双端口帧存储器写入数据的软件应用程序，并通过第二访问端口从双端口帧存储器读取数据。
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公开(公告)号：US20090175205A1
公开(公告)日：2009-07-09
申请号：US12199640
申请日：2008-08-27
Applicant: Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
Inventor： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
CPC classification number: G06F15/7842 , H04L1/0045 , H04L1/0052 , H04L1/1829
Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
Abstract translation: 一种用于在无线系统中处理信号的装置包括用于从一组物理信道接收输入数据的第一存储器模块，用于处理输入数据的第一多个子模块。 第一多个子模块中的每一个被选择为基于数据和传输信道规范起作用。 该装置还包括用于接收经处理的输入数据和输出中间数据的第二存储器模块。 第二存储器中的输入数据的位置与数据和传输通道规范相关联地被分配。 该装置还包括用于处理中间数据的第二多个子模块。 第二多个子模块中的每一个被选择为基于数据和传输信道规范起作用。 该装置还包括用于接收和输出比特率处理输出的第三存储器模块。
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公开(公告)号：US20090161647A1
公开(公告)日：2009-06-25
申请号：US12194512
申请日：2008-08-19
Applicant: Russ Mestechkin , Deepak Mathew , Justin Wang , Sanjay Nandipaku
Inventor： Russ Mestechkin , Deepak Mathew , Justin Wang , Sanjay Nandipaku
CPC classification number: H04B1/707 , H04B2201/70707
Abstract: A wireless system has an uplink chip rate processing architecture in which at least two groups of registers are provided, each group of register storing a set of time slot configuration parameters. A storage stores a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot. A chip rate processing unit processes a stream of data over a plurality of time slots in which at each of the time slots, and the chip rate processing unit is configured according to the set of time slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot.
Abstract translation: 无线系统具有其中提供至少两组寄存器的上行链路码片速率处理架构，每组寄存器存储一组时隙配置参数。 存储器存储一系列时隙配置集标识符，每个识别寄存器组中的一个，每个标识符对应于时隙。 芯片速率处理单元在多个时隙中处理数据流，其中在每个时隙中，并且根据存储在与所述时隙相关联的寄存器组中的时隙配置参数的集合来配置码片速率处理单元 时隙配置设置标识符对应于该时隙。
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