Abstract:
One of the problems in display devices is that the black level is different for each type of display tube and is also dependent on temperature and ageing. The display devices hitherto known with black level setting circuits apply one control voltage to the relevant cathode during the field blanking interval, whereafter the cathode current is measured and subsequently compared with a reference current. Subsequently, the black level is adapted until the measured current approximately corresponds to the reference current.The display device now includes a black level setting circuit with a control circuit adapted to successively apply at least two control voltages in a predetermined ratio to the cathode. Moreover, the black level setting circuit includes a correction circuit for supplying a correction value dependent on the ratio between the currents generated in the relevant cathode in response to the at least two control voltages.
Abstract:
A picture display device, having a line synchronizing circuit and a line deflection circuit, suitable for several line frequencies. Use is made of a modulator for modulating the line deflection current, a control stage being coupled to this modulator for applying a correction signal for correcting, in dependence on the frequency of a line oscillator in the line synchronizing circuit, the S-distortion or the linearity error, respectively, or to keep the amplitude of the line deflection current constant upon a change in the line frequency.
Abstract:
A circuit arrangement for generating a sawtooth-shaped signal for the field deflection in a picture display device with an amplitude which is substantially independent of the field frequency is disclosed. The value of the sawtooth-shaped signal during the occurrence of a sampling pulse is compared with a reference value for generating a control signal controlling the slope of the sawtooth-shaped signal. To eliminate instability in amplitude, which might result from phase jitter of the incoming field synchronizing signal and might cause an interlace error, sampling pulses are applied whose repetition frequency is substantially equal to the nth part of the field frequency, where n is an integer which is larger than 1, preferably a small multiple of 2.
Abstract:
A circuit arrangement comprising at least two high-voltage power switches (e.g. transistors) connected in series to a high voltage source. In order to ensure that the switches are automatically cut off substantially simultaneously, the control means of each switch comprise a delay element for delaying the cut-off signal. A comparison stage controls the delay caused by at least one delay element as a function of the difference between the voltage present at the junction point of the switches and a reference voltage.