公开(公告)号：US20110309885A1

公开(公告)日：2011-12-22

申请号：US12878476

申请日：2010-09-09

Applicant: Myeung Su KIM ,  Han Jin CHO ,  Joon Hyung LIM ,  Kyung Hee HONG ,  Yong Il KWON

Inventor： Myeung Su KIM ,  Han Jin CHO ,  Joon Hyung LIM ,  Kyung Hee HONG ,  Yong Il KWON

IPC: H03K3/03

CPC classification number: H03K3/0322 ,  H03K3/012

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract translation: 这里公开了一种用于低功率环形振荡器的延迟电路。 延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

公开(公告)号：US07830959B2

公开(公告)日：2010-11-09

申请号：US10876739

申请日：2004-06-28

Applicant: Seong Mo Park ,  Seung Chul Kim ,  Mi Young Lee ,  Han Jin Cho ,  Jong Dae Kim

Inventor： Seong Mo Park ,  Seung Chul Kim ,  Mi Young Lee ,  Han Jin Cho ,  Jong Dae Kim

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04

CPC classification number: H04N19/436 ,  H04N19/105 ,  H04N19/186 ,  H04N19/423 ,  H04N19/44 ,  H04N19/593

Abstract: Provided is an apparatus and method for performing intra prediction for an image decoder, in which by use of horizontal/vertical blocks adjacent to image data input from an external device, the intra prediction is performed in parallel with respect to 16×16 luminance component and 4×4 luminance component of the image data and then with respect to chrominance component, thereby maximizing efficiency of system to not only reduce execution time and hardware cost but also increase processing speed.

Abstract translation: 提供了一种用于对图像解码器进行帧内预测的装置和方法，其中通过使用与从外部设备输入的图像数据相邻的水平/垂直块，相对于16×16亮度分量并行执行帧内预测， 图像数据的4×4亮度分量，然后相对于色度分量，从而最大化系统的效率，不仅减少了执行时间和硬件成本，而且提高了处理速度。

公开(公告)号：US20100150041A1

公开(公告)日：2010-06-17

申请号：US12430313

申请日：2009-04-27

Applicant: Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

Inventor： Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

IPC: G08C17/00

CPC classification number: H04Q9/02 ,  H04Q2209/43 ,  H04Q2209/883

Abstract: Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.

Abstract translation: 公开了一种具有自感功能的无线通信装置，其可以通过使用唤醒功能而不使用单独的传感器来检测对象。 该无线通信装置包括与形成无线网络的服务器无线通信的通信单元，以及当通信单元处于睡眠模式时，在服务器的控制下唤醒通信单元的唤醒单元，并且感测到 根据反射信号在预设通信范围内对象，该反射信号是从通信单元发送之后由对象反射的信号。

公开(公告)号：US07554355B2

公开(公告)日：2009-06-30

申请号：US11607515

申请日：2006-12-01

Applicant: June Young Chang ,  Han Jin Cho

Inventor： June Young Chang ,  Han Jin Cho

IPC: H04L12/50 ,  H03K17/00

CPC classification number: H04L49/101 ,  H04L49/15 ,  H04L49/45

Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Abstract translation: 提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易 增加并具有简单的控制结构。 交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与 每行最后一列的多路复用器与该行的输入/输出线连接。

公开(公告)号：US20080111820A1

公开(公告)日：2008-05-15

申请号：US11933060

申请日：2007-10-31

Applicant: June-Young Chang ,  Han-Jin Cho

Inventor： June-Young Chang ,  Han-Jin Cho

IPC: G06F15/16

CPC classification number: H04N19/436 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44

Abstract: Provided is an On-Chip network (OCN) based moving picture decoder. The moving picture decoder includes: a plurality of switches for providing a parallel data transmission path between a predetermined master module and the other master module, a parallel data transmission path between a predetermined master module and a predetermined slave module, and a parallel data transmission path between a predetermined slave module and the other slave module; and a plurality of On-Chip Networks (OCNs) for providing a local parallel data transmission path between predetermined slave modules and a parallel data transmission path between a slave module in a corresponding area and the switches, wherein a OCN structure of the moving picture decoder globally has a mesh structure with the switches as medium and locally has a star structure with each of the ONCs as medium.

Abstract translation: 提供了一种基于片上网络（OCN）的运动图像解码器。 运动图像解码器包括：用于在预定主模块和另一主模块之间提供并行数据传输路径的多个开关，预定主模块和预定从模块之间的并行数据传输路径以及并行数据传输路径 在预定的从模块和另一个从模块之间; 以及多个片上网络（OCN），用于在预定的从模块之间提供本地并行数据传输路径，以及在相应区域中的从模块与开关之间的并行数据传输路径，其中运动图像解码器的OCN结构 全局具有网状结构，开关为介质，局部具有星形结构，每个ONC为介质。

公开(公告)号：US06888904B2

公开(公告)日：2005-05-03

申请号：US09866277

申请日：2001-05-24

Applicant: In-Gi Lim ,  Suk-Ho Lee ,  Kyung-Soo Kim ,  Han-Jin Cho

Inventor： In-Gi Lim ,  Suk-Ho Lee ,  Kyung-Soo Kim ,  Han-Jin Cho

IPC: H04L27/30 ,  H03H17/06 ,  H03K5/159 ,  G06F17/17

CPC classification number: H03H17/0621 ,  H03H17/0607

Abstract: A 108-tap 1:4 interpolation FIR filter device for digital mobile telecommunication having a single bit input that employs a look-up table minimum scheme and a pipeline structure in which the size of the entire look-up tables is significantly reduced by dividing four coefficient groups into three parts, respectively, and effectively using the symmetry of the 108-tap filter coefficient and the symmetry within the look-up table. The FIR filter includes an input shift register and selector for processing a single bit input of four channels, an address generator for producing addresses of the look-up table, look-up table group 0˜3 for producing filter outputs group by group via the look-up table and the calculator using the address as an input, a pipeline register I for delaying the filter outputs for coefficient group which are outputted in parallel, a group selector for converting the delayed outputs in serial channel by channel, and a pipeline register II for matching the time of filter output channel by channel.

Abstract translation: 具有使用查找表最小方案的单个位输入的数字移动通信的108抽头1：4内插FIR滤波器装置和通过将四个整数查找表的大小分开来显着减少整个查找表的大小的流水线结构 系数组分别分为三部分，并有效地利用了108抽头滤波器系数的对称性和查找表中的对称性。 FIR滤波器包括用于处理四个通道的单个位输入的输入移位寄存器和选择器，用于产生查找表的地址的地址发生器，用于通过组播逐个产生滤波器输出的查找表组0〜3 查找表和使用地址作为输入的计算器，用于延迟并行输出的系数组的滤波器输出的流水线寄存器I，用于逐个逐个逐个通道转换延迟输出的组选择器和流水线寄存器 II用于匹配滤波器输出通道的时间。

公开(公告)号：US06850569B2

公开(公告)日：2005-02-01

申请号：US09846153

申请日：2001-04-30

Applicant: Seong-Mo Park ,  Ju-Hyun Park ,  Jin-Jong Cha ,  Han-Jin Cho

Inventor： Seong-Mo Park ,  Ju-Hyun Park ,  Jin-Jong Cha ,  Han-Jin Cho

IPC: H04N7/32 ,  G06T7/20 ,  H04N5/14 ,  H04N7/26 ,  H04N7/12

CPC classification number: H04N5/145 ,  G06T7/207 ,  H04N19/53

Abstract: In the present invention, a reference block data within a current image from which a motion vector will be obtained and corresponding search region data within reproduced previous image are stored in a reference block and a search region data memory, respectively. A motion vector of two pixels unit is performed using the reference block and the search region data stored in the memory, thus resulting in obtained a motion vector of two pixels unit. At this time, the reference block and the search region data are used by performing 2:1 sampling in a horizontal direction and a vertical direction, respectively and the search range is −7˜+7. The structure of the motion search is consisted of a memory for storing a reference block (8×8) of current images and a memory (24×8) for storing a search region storing reproduced previous images. The structure further includes a processing element (PE) array block for obtaining SAD (sum of absolute difference) among candidate blocks within the search region and a block for obtaining the smallest motion vector among the candidate SADs. If hardware is implemented using the two-step search algorithm among the motion estimation of the present invention, a lot of data bandwidth of the reference memory and a memory having a large size are required. The down sampling scheme and the bandwidth of the reference memory has a structure in which a slice is previously downloaded before a pipeline when it downloads from the external memory. In an actual pipeline operation, it is implemented by the bandwidth of ⅓. Also, as it has independent memories, it can operate even at low frequency without degrading the performance.

Abstract translation: 在本发明中，分别在参考块和搜索区域数据存储器中分别存储当前图像中的将获得运动矢量的参考块数据和再现的先前图像内的相应搜索区域数据。 使用存储在存储器中的参考块和搜索区域数据来执行两个像素单元的运动矢量，从而得到两个像素单位的运动矢量。 此时，通过在水平方向和垂直方向上分别进行2:1的采样来使用参考块和搜索区域数据，并且搜索范围为-7〜+ 7。 运动搜索的结构由用于存储当前图像的参考块（8×8）的存储器和用于存储存储再现的先前图像的搜索区域的存储器（24x8）组成。 该结构还包括处理元件（PE）阵列块，用于获得搜索区域内的候选块之间的SAD（绝对差之和）和用于获得候选SAD之间的最小运动矢量的块。 如果在本发明的运动估计中使用两步搜索算法实现硬件，则需要参考存储器的大量数据带宽和大尺寸的存储器。 下采样方案和参考存储器的带宽具有这样的结构，其中当从外部存储器下载时，管线之前预先下载片。 在实际流水线操作中，以1/3的带宽实现。 此外，由于它具有独立的存储器，所以即使在低频下也可以运行，而不会降低性能。

公开(公告)号：US5995593A

公开(公告)日：1999-11-30

申请号：US841604

申请日：1997-04-30

Applicant: Han-Jin Cho

Inventor： Han-Jin Cho

IPC: H04B10/02 ,  H04M11/00 ,  H04B1/38

CPC classification number: H04M11/002

Abstract: A wire/wireless communication system includes two units for wire/wireless communication of information using a telephone network between two locations which are far away from each other. One of the two units is a data transmitting unit, such as a computer terminal, which is positioned at a first location and the other is a data receiving unit. To the units, infrared transceivers are coupled to transmit information as infrared radiation and receive the infrared radiation. Also, to the data transmitting and receiving units, telephones are connected. These telephones are interconnected by the telephone network therebetween and are respectively connected to transceivers. Wireless communication between the computer terminal of the data transmitting unit and the telephone which are positioned at the first location may be accomplished by the transceivers respectively coupled to them. The electrical signal corresponding to the information from the computer terminal is supplied through the telephone network to the telephone which is positioned adjacent to the computer terminal at the second location.

Abstract translation: 有线/无线通信系统包括两个单元，用于使用彼此远离的两个位置之间的电话网络进行信息的有线/无线通信。 两个单元中的一个是诸如计算机终端的数据发送单元，其位于第一位置，而另一个是数据接收单元。 对于这些单元，红外收发器被耦合以作为红外辐射传送信息并接收红外辐射。 而且，数据发送和接收单元连接有电话。 这些电话通过它们之间的电话网互连，并分别连接到收发器。 数据发送单元的计算机终端与位于第一位置的电话之间的无线通信可以由分别耦合到它们的收发器来实现。 对应于来自计算机终端的信息的电信号通过电话网络提供给位于第二位置处与计算机终端相邻的电话。

公开(公告)号：US5864300A

公开(公告)日：1999-01-26

申请号：US753685

申请日：1996-11-27

Applicant: Han-Jin Cho ,  Young-Gyoo Choi

Inventor： Han-Jin Cho ,  Young-Gyoo Choi

IPC: H04L29/04 ,  H04B7/00 ,  H04L12/28 ,  H04L12/66 ,  H04L29/06 ,  H04W48/18 ,  H04W88/06 ,  H04Q5/22 ,  G06F12/00 ,  H01J9/00

CPC classification number: H04W48/18 ,  H04W88/06

Abstract: A wireless communication system and process for transmission of data communications, may be practiced with a microprocessor, a memory, a controller, a selector and a communication block, and the effect of the wireless communication system for selecting a communication transmission method lies in the fact that a user can select a wireless communication device according to user's needs in a wireless communication device having at least one communication transmission method or a plurality of wireless communication devices having different communication transmission methods, using only one controller.

Abstract translation: 用于传输数据通信的无线通信系统和过程可以用微处理器，存储器，控制器，选择器和通信块来实现，并且用于选择通信传输方法的无线通信系统的效果在于事实 使用者只要使用一个控制器就可以根据用户的需要选择具有至少一种通信传输方式的无线通信设备或具有不同通信传输方式的多个无线通信设备的无线通信设备。

公开(公告)号：US5596287A

公开(公告)日：1997-01-21

申请号：US343890

申请日：1994-11-16

Applicant: Han-Jin Cho

Inventor： Han-Jin Cho

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1737

Abstract: A logic module for embodying a wide combination of logic and sequential logic in response to a user's demand is divided into a combination circuit part and a sequential circuit part. The combination circuit part is divided into a first stage including a first and a second two-input multiplexers and a second stage. The respective input terminals of the first and second multiplexers are connected to output terminals of two-input AND gates and a first and second input terminals of the two-input AND gates are data and inverted data to select the desired data state. The respective first and second multiplexers have select control input terminals which are connected to an output of an exclusive OR gate having two inputs. The second stage of the combination circuit part includes a third two-input multiplexer of which the first input is connected to the output of the first multiplexer, and a second input is connected to the output of the second multiplexer and a data select control input is connected to an output of a four-input logic gate. The four-input logic gate has two data inputs and two inverted data inputs, thereby embodying the AND combination of two data on demand. The sequential circuit part of a logic module consists of a switching part and a sequential part. The one of outputs from the first and second multiplexers of the combination circuit part is directly selected by the switching part.

Abstract translation: 用于根据用户需求实现逻辑和顺序逻辑的广泛组合的逻辑模块被分为组合电路部分和顺序电路部分。 组合电路部分被分为包括第一和第二双输入多路复用器的第一级和第二级。 第一和第二多路复用器的各个输入端连接到双输入与门的输出端，双输入与门的第一和第二输入端是数据和反相数据，以选择所需的数据状态。 各自的第一和第二多路复用器具有连接到具有两个输入的异或门的输出的选择控制输入端。 组合电路部分的第二级包括第三双输入多路复用器，其中第一输入连接到第一多路复用器的输出，第二输入连接到第二多路复用器的输出，数据选择控制输入为 连接到四输入逻辑门的输出。 四输入逻辑门具有两个数据输入和两个反相数据输入，从而体现了两个数据按需的AND组合。 逻辑模块的顺序电路部分由切换部分和顺序部分组成。 来自组合电路部分的第一和第二多路复用器的输出之一由切换部分直接选择。