公开(公告)号：US07565558B2

公开(公告)日：2009-07-21

申请号：US11409974

申请日：2006-04-25

Applicant: Wen Juin Huang ,  Chung-Ching Huang ,  Hao Lin Lin ,  Yeh Cho

Inventor： Wen Juin Huang ,  Chung-Ching Huang ,  Hao Lin Lin ,  Yeh Cho

IPC: G06F1/00 ,  G06F1/32 ,  G06F13/00

CPC classification number: G06F1/3203

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Abstract translation: 公开了一种省电方法及其系统。 当中央处理单元处于非窥探睡眠状态并且外围设备发送总线主机请求时，芯片将驱动中央处理单元从非窥探睡眠状态唤醒并进入用于执行中断服务的系统管理模式 使中央处理单元处于停止状态的程序。 然后中央处理单元被驱动以进入窥探睡眠状态以窥探总线主控请求。 执行总线主机请求后，芯片将驱动中央处理单元离开窥探睡眠状态，并返回到非窥探睡眠状态，以实现功耗节省。

公开(公告)号：US07296185B2

公开(公告)日：2007-11-13

申请号：US10820768

申请日：2004-04-09

Applicant: Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F11/00

CPC classification number: G06F11/362

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract translation: 提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。 调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。 然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。 每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。 在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。 调试的执行不会影响操作系统的状态和程序的执行。 所公开的调试方法可以随时执行每个调试项目。

公开(公告)号：US07930532B2

公开(公告)日：2011-04-19

申请号：US11861335

申请日：2007-09-26

Applicant: Hao-Lin Lin ,  Hsiao-Fung Chou

Inventor： Hao-Lin Lin ,  Hsiao-Fung Chou

IPC: G06F9/00 ,  G06F15/177

CPC classification number: G06F13/4072

Abstract: An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.

Abstract translation: 计算机系统的一个实施例包括一个南桥。 南桥包括一个包括与电子设备进行通信的缓冲器的控制器。 当检测到Reset＃信号被断言时，缓冲器被设置为Hi-Impedance状态以将控制器与电子设备分离。 Reset＃信号表示完整的系统复位。

公开(公告)号：US20100131748A1

公开(公告)日：2010-05-27

申请号：US12624846

申请日：2009-11-24

Applicant: Hao-Lin Lin

Inventor： Hao-Lin Lin

IPC: G06F15/177 ,  G06F12/00

CPC classification number: G06F3/0658 ,  G06F3/0625 ,  G06F3/0626 ,  G06F3/0679 ,  Y02D10/154

Abstract: A computer system with integrated storage device for storing both a basic input/output system (BIOS) code and an operating system (OS) code and an associated booting method are provided. The computer system includes a central processing unit, a storage device controller and the storage device. The BIOS code and the OS code are stored in an invisible are and a visible area of the storage device, respectively. At first, the storage device controller is activated to read data from an architecture information area of the storage device to perform initialization. Then, the initialized storage device controller converts a read-only memory access command issued from the central processing unit into a suitable format to control loading of the BIOS code from the invisible area. At last, the storage device controller controls loading of the OS code from the visible area to finish the booting of the computer system.

Abstract translation: 提供一种具有用于存储基本输入/输出系统（BIOS）代码和操作系统（OS）代码和相关联的引导方法的集成存储设备的计算机系统。 计算机系统包括中央处理单元，存储设备控制器和存储设备。 BIOS代码和OS代码分别存储在存储设备的不可见区域和可见区域中。 首先，存储设备控制器被激活以从存储设备的架构信息区域读取数据以执行初始化。 然后，初始化的存储装置控制器将从中央处理单元发出的只读存储器访问命令转换成适当的格式，以控制来自不可见区域的BIOS代码的加载。 最后，存储设备控制器控制OS可视区域的加载，完成计算机系统的启动。