公开(公告)号：US20080018651A1

公开(公告)日：2008-01-24

申请号：US11522900

申请日：2006-09-19

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F15/00

CPC classification number: G06F11/0787 ,  G06F11/0706

Abstract: A method for capturing an image data from a frame buffer of a computer system takes advantage of a system management interrupt service optionally triggered. If a storage unit functions normally when the computer system fails to work normally, store the image data in the frame buffer into the storage unit. Otherwise, temporarily store the image data in a buffer unit, and then store it in a NVRAM. Then restart the storage unit and restore the image data in the buffer unit into the storage unit. At last, restart the computer system.

Abstract translation: 用于从计算机系统的帧缓冲器捕获图像数据的方法利用可选地触发的系统管理中断服务。 如果计算机系统无法正常工作时存储单元正常工作，则将帧缓冲区中的图像数据存储到存储单元中。 否则，将图像数据临时存储在缓冲单元中，然后将其存储在NVRAM中。 然后重新启动存储单元，并将缓冲单元中的图像数据恢复到存储单元中。 最后重新启动计算机系统。

公开(公告)号：US07565558B2

公开(公告)日：2009-07-21

申请号：US11409974

申请日：2006-04-25

Applicant: Wen Juin Huang ,  Chung-Ching Huang ,  Hao Lin Lin ,  Yeh Cho

Inventor： Wen Juin Huang ,  Chung-Ching Huang ,  Hao Lin Lin ,  Yeh Cho

IPC: G06F1/00 ,  G06F1/32 ,  G06F13/00

CPC classification number: G06F1/3203

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Abstract translation: 公开了一种省电方法及其系统。 当中央处理单元处于非窥探睡眠状态并且外围设备发送总线主机请求时，芯片将驱动中央处理单元从非窥探睡眠状态唤醒并进入用于执行中断服务的系统管理模式 使中央处理单元处于停止状态的程序。 然后中央处理单元被驱动以进入窥探睡眠状态以窥探总线主控请求。 执行总线主机请求后，芯片将驱动中央处理单元离开窥探睡眠状态，并返回到非窥探睡眠状态，以实现功耗节省。

公开(公告)号：US07296185B2

公开(公告)日：2007-11-13

申请号：US10820768

申请日：2004-04-09

Applicant: Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F11/00

CPC classification number: G06F11/362

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract translation: 提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。 调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。 然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。 每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。 在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。 调试的执行不会影响操作系统的状态和程序的执行。 所公开的调试方法可以随时执行每个调试项目。

公开(公告)号：US20050154803A1

公开(公告)日：2005-07-14

申请号：US11009881

申请日：2004-12-10

Applicant: Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

IPC: G06F12/00 ,  G06F13/10 ,  G06F13/28

CPC classification number: G06F13/102

Abstract: A method for accessing a memory of a computer system for BIOS codes optionally performs a detection procedure to realize a maximum memory burst read size of the memory according to a flag value upon the computer system is initialized. For example, the detection procedure is performed when the flag value is logic “1” and the detection procedure is not performed when the flag value is logic “0”. When the detection procedure is performed, read requests with sequentially reduced memory burst read sizes are asserted to the memory one by one until the maximum memory burst read size of the memory is realized. Then, the BIOS codes are read from the memory with the maximum memory burst read size.

Abstract translation: 用于访问用于BIOS代码的计算机系统的存储器的方法可选地执行检测过程，以在计算机系统初始化时根据标志值实现存储器的最大存储器突发读取大小。 例如，当标志值为逻辑“1”时执行检测过程，并且当标志值为逻辑“0”时不执行检测过程。 当执行检测过程时，依次减少的存储器突发读取大小的读取请求被逐个断言给存储器，直到实现存储器的最大存储器突发读取大小。 然后，从具有最大存储突发读取大小的存储器中读取BIOS代码。

公开(公告)号：US20050060617A1

公开(公告)日：2005-03-17

申请号：US10820768

申请日：2004-04-09

Applicant: Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F11/00

CPC classification number: G06F11/362

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract translation: 提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。 调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。 然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。 每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。 在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。 调试的执行不会影响操作系统的状态和程序的执行。 所公开的调试方法可以随时执行每个调试项目。

公开(公告)号：US20070208929A1

公开(公告)日：2007-09-06

申请号：US11560924

申请日：2006-11-17

Applicant: Hao-Lin Lin ,  Chung-Ching Huang

Inventor： Hao-Lin Lin ,  Chung-Ching Huang

IPC: G06F9/00

CPC classification number: G06F9/4411

Abstract: A device information management system comprises an application device and a BIOS ROM. The BIOS ROM comprises at least one specific region storing device information for the application device. The specific region is not used by a BIOS and not within a calculation range for checksum calculation. The BIOS ROM further comprises an index recording an address of the specific region. The application device reads the index from the BIOS ROM, and reads the device information from the specific region according to the index.

Abstract translation: 设备信息管理系统包括应用设备和BIOS ROM。 BIOS ROM包括用于应用设备的至少一个特定区域存储设备信息。 特定区域不被BIOS使用，不在校验和计算的计算范围内。 BIOS ROM还包括记录特定区域的地址的索引。 应用程序设备从BIOS ROM读取索引，并根据索引从特定区域读取设备信息。

公开(公告)号：US08607084B2

公开(公告)日：2013-12-10

申请号：US13115792

申请日：2011-05-25

Applicant: Chung-Ching Huang ,  Kuo-Han Chang ,  Chih-Nan Lo ,  Donna Lim

Inventor： Chung-Ching Huang ,  Kuo-Han Chang ,  Chih-Nan Lo ,  Donna Lim

IPC: G06F1/26 ,  G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A computer system and a power-management method thereof are provided. The computer system has an image-reading mode, a first power-management mode and a second power-management mode, and the computer system operating in the second power-management mode consumes less power than it consumes in the first power-management mode. The computer system comprises a first portion comprising a graphics processing unit, a memory space and a display; and a second portion comprising a storage storing an image data. When the computer system operates in the image-reading mode, the image data has been transferred to the memory space from the storage, the second portion enters to the second power-management mode from the first power-management mode, and the first portion keeps in the first power-management mode, so that the graphics processing unit can display an image by the display according to the image data stored in the memory space.

Abstract translation: 提供了一种计算机系统及其电源管理方法。 计算机系统具有图像读取模式，第一功率管理模式和第二功率管理模式，并且在第二功率管理模式下操作的计算机系统比在第一功率管理模式中消耗的功率消耗更少的功率。 计算机系统包括第一部分，包括图形处理单元，存储器空间和显示器; 以及第二部分，包括存储图像数据的存储器。 当计算机系统以图像读取模式操作时，图像数据已经从存储器传送到存储器空间，第二部分从第一电力管理模式进入第二电力管理模式，并且第一部分保持 在第一电源管理模式中，使得图形处理单元可以根据存储在存储器空间中的图像数据通过显示来显示图像。

公开(公告)号：US20100199022A1

公开(公告)日：2010-08-05

申请号：US12401133

申请日：2009-03-10

Applicant: Chun-Hsu Chen ,  Chung-Ching Huang ,  Chin-Han Chang

Inventor： Chun-Hsu Chen ,  Chung-Ching Huang ,  Chin-Han Chang

IPC: G06F12/02

CPC classification number: G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: An information access method and a computer system are provided. The computer system includes a system management bus (SMBus), a non-volatile memory, a plurality of hardware devices, a chipset, and a CPU. The hardware devices have a plurality of specific recognition information. The CPU performs a configuration process on the hardware devices through the chipset according to the standard for a SMBus protocol, so as to distribute a plurality of memory spaces in the non-volatile memory to the hardware devices. The hardware devices share the SMBus for accessing the plurality of specific recognition information in the memory spaces.

Abstract translation: 提供信息访问方法和计算机系统。 计算机系统包括系统管理总线（SMBus），非易失性存储器，多个硬件设备，芯片组和CPU。 硬件设备具有多个特定识别信息。 CPU根据SMBus协议的标准通过芯片组对硬件设备执行配置处理，以将非易失性存储器中的多个存储空间分配给硬件设备。 硬件设备共享SMBus以访问存储器空间中的多个特定识别信息。

公开(公告)号：US20070088879A1

公开(公告)日：2007-04-19

申请号：US11538693

申请日：2006-10-04

Applicant: Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

Inventor： Chung-Ching Huang ,  Ta-Chuan Liu ,  Tzu-Chiang Chiu ,  Chin-Fa Hsiao

IPC: G06F13/12

CPC classification number: G06F13/385

Abstract: In a method used for initializing a first bus device and a second bus device sharing a common transmission engine of a bus, a first link of the first bus device and a second link of the second bus device to the common transmission engine are disabled when the computer system is booted. Next, the first link and the second link are enabled in order. Then, a first state updating signal from the first bus device is issued after the first link to the common transmission engine is established. Finally, a second state updating signal from the second bus device is issued after the first state updating signal is received and the second link to the common transmission engine is established.

Abstract translation: 在用于初始化共享总线的公共传输引擎的第一总线设备和第二总线设备的方法中，当第一总线设备的第一链路和第二总线设备的第二链路到公共传输引擎时，当第 计算机系统启动。 接下来，按顺序启用第一个链接和第二个链接。 然后，在建立到公共传输引擎的第一链路之后，发出来自第一总线设备的第一状态更新信号。 最后，在接收到第一状态更新信号并建立到公共传输引擎的第二链路之后，发出来自第二总线设备的第二状态更新信号。

公开(公告)号：US07162568B2

公开(公告)日：2007-01-09

申请号：US10757464

申请日：2004-01-15

Applicant: Chung-Ching Huang ,  Kuan-Jui Ho

Inventor： Chung-Ching Huang ,  Kuan-Jui Ho

IPC: G06F12/00

CPC classification number: G06F11/2284

Abstract: An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising an identity and an address range associated with a flash ROM. The strapping component is configured to output a signal to determine flash ROM type. The process unit receives a memory access request with an access range from the CPU and the signal from the strapping component queries the identity by matching the access range and the address range, and finally executes an LPC 1.1 memory access instruction with the identity and the access range corresponding to the memory cycle.

Abstract translation: 一种闪存ROM管理的设备和方法。 该装置包括存储装置，捆扎部件和处理单元。 存储设备存储包括与快闪ROM相关联的身份和地址范围的多个地址记录。 绑带组件配置为输出信号以确定闪存ROM类型。 处理单元从CPU接收具有访问范围的存储器访问请求，并且来自绑带组件的信号通过匹配访问范围和地址范围来查询身份，并且最终执行具有身份和访问权的LPC 1.1存储器访问指令 范围对应于存储器周期。