公开(公告)号：US5854560A

公开(公告)日：1998-12-29

申请号：US749360

申请日：1996-11-20

申请人： Hwang-Cherng Chow

发明人： Hwang-Cherng Chow

IPC分类号： H03K19/003 ,  H03K19/0948 ,  H03K17/16

CPC分类号： H03K19/00361

摘要： In a preferred embodiment of the present invention an output buffer includes high current drivers that avoids a short circuit current. Further, the inventive output buffer only produces a slight level of ground bounce (noise). In particular, the buffer comprises first and second drivers for driving a terminal to a voltage corresponding to a high logic value of a first output signal and a low logic value of a second output signal, respectively. Typically, the first driver includes a plurality of PMOS pull-up transistors and the second driver includes a plurality of NMOS pull-down transistors. In addition, first and second predriver circuits, connected to the first and second drivers, respectively, are included. In operation, the first predriver receives the complement (inverse) of the first output signal and a delayed output of the second predriver. The second predriver receives the complement of the second output signal and the delayed output of the first predriver. In this manner, all pull-up (or pull-down) transistors are completely turned on before the pull-down (or pull-up) transistors are sequentially turned off. Therefore, a short-circuit current that may occur during a logic transition in the output signal is eliminated.

摘要翻译： 在本发明的优选实施例中，输出缓冲器包括避免短路电流的高电流驱动器。 此外，本发明的输出缓冲器仅产生轻微的地面反弹（噪声）水平。 特别地，缓冲器包括分别用于将终端驱动到对应于第一输出信号的高逻辑值和第二输出信号的低逻辑值的电压的第一和第二驱动器。 通常，第一驱动器包括多个PMOS上拉晶体管，第二驱动器包括多个NMOS下拉晶体管。 此外，包括分别连接到第一和第二驱动器的第一和第二预驱动电路。 在操作中，第一预驱动器接收第一输出信号的补码（反）和第二预驱动器的延迟输出。 第二预驱动器接收第二输出信号的补码和第一预驱动器的延迟输出。 以这种方式，在下拉（或上拉）晶体管依次关闭之前，所有上拉（或下拉）晶体管完全导通。 因此，消除了在输出信号的逻辑转换期间可能发生的短路电流。

公开(公告)号：US5808492A

公开(公告)日：1998-09-15

申请号：US623350

申请日：1996-03-28

申请人： Hwang-Cherng Chow

发明人： Hwang-Cherng Chow

IPC分类号： H03K17/16

CPC分类号： H03K17/164

摘要： A bidirectional buffer circuit is provided with a terminal, an input buffer, a steady state output driver and a strong output driver. The input buffer is for receiving an input signal from the terminal. The steady state output driver includes a weak driver for driving the terminal to a first voltage corresponding to a first particular logic value of the output signal. The weak driver has a limited driving capacity that can be out-driven by the input signal. The strong output driver is for driving the terminal to the first voltage. The strong output driver has a greater driving capacity than the weak output driver. Enable circuitry is also provided. The enable circuitry includes at least one delay circuit with a particular delay period. The enable circuitry enables the strong output driver in response to a transition of the output signal from a complement of the first logic value to the first logic value. However, the enable circuitry only enables the strong driver during the delay period of the delay element.

摘要翻译： 双向缓冲电路具有端子，输入缓冲器，稳态输出驱动器和强输出驱动器。 输入缓冲器用于从终端接收输入信号。 稳态输出驱动器包括用于将终端驱动到对应于输出信号的第一特定逻辑值的第一电压的弱驱动器。 弱驱动器的驱动能力有限，可以通过输入信号驱动。 强大的输出驱动器是将端子驱动到第一个电压。 强大的输出驱动器具有比弱输出驱动器更大的驱动能力。 还提供启用电路。 使能电路包括具有特定延迟周期的至少一个延迟电路。 使能电路使得强输出驱动器响应于从第一逻辑值的补码到第一逻辑值的输出信号的转变。 然而，使能电路仅在延迟元件的延迟周期期间使能强驱动器。

公开(公告)号：US5757242A

公开(公告)日：1998-05-26

申请号：US762662

申请日：1996-12-09

申请人： Hwang-Cherng Chow ,  Tain-Shun Wu

发明人： Hwang-Cherng Chow ,  Tain-Shun Wu

IPC分类号： H03B5/36 ,  H03K3/03 ,  H03K3/354 ,  H03B5/02

CPC分类号： H03K3/3545 ,  H03K3/0307 ,  H03B5/364

摘要： A low power consumption oscillator circuit is provided with an oscillator. The oscillator responds to a voltage by producing an oscillating signal at its output having an amplitude that depends on the level of the voltage. Furthermore, the low power consumption oscillator circuit has a level shifter. Illustratively, according to one embodiment, the level shifter includes a pull-up driver and a pull-down driver connected in parallel between the oscillator output and an output of the level shifter. The pull-up driver is configured so as to refrain from conducting current between a biasing input of the pull-up driver and the level shifter output simultaneously with the pull-down driver when the oscillating signal exceeds a certain voltage level. The level shifter illustratively includes an intrinsic PMOS device.

摘要翻译： 低功耗振荡器电路配有振荡器。 振荡器通过在其输出处产生具有取决于电压电平的幅度的振荡信号来响应电压。 此外，低功耗振荡器电路具有电平移位器。 示例性地，根据一个实施例，电平移位器包括并联连接在振荡器输出和电平转换器的输出之间的上拉驱动器和下拉驱动器。 上拉驱动器被配置为当振荡信号超过一定电压电平时，避免在上拉驱动器的偏置输入和电平移位器输出同时与下拉驱动器之间导通电流。 电平移位器示例性地包括固有PMOS器件。

公开(公告)号：US6094086A

公开(公告)日：2000-07-25

申请号：US855844

申请日：1997-05-12

申请人： Hwang-Cherng Chow

发明人： Hwang-Cherng Chow

IPC分类号： H03K17/16 ,  H03K17/296

CPC分类号： H03K17/164

摘要： An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The second driver has a greater (current) driving capacity than the first driver. The output buffer also has control circuitry which detects a transition in the logic value of the input signal. In response, the control circuitry generates a particular pulse aligned with the input signal logic value transition having a particular constant voltage level for a predetermined time period. Furthermore, the control circuitry delays the second circuit from driving the output terminal to a complementary voltage level corresponding to the logic value to which the input signal transitions during the predetermined time period.

摘要翻译： 提供输出缓冲器，其接收输入信号并驱动输出端子。 输出缓冲器具有用于将输出端驱动到与输入信号的逻辑值对应的电压电平的第一驱动器和第二驱动器。 第二个驾驶员的驾驶能力比第一个驾驶员要大（目前）。 输出缓冲器还具有检测输入信号的逻辑值中的转换的控制电路。 作为响应，控制电路产生与预定时间段具有特定恒定电压电平的输入信号逻辑值转换对准的特定脉冲。 此外，控制电路延迟第二电路驱动输出端子到对应于在预定时间段期间输入信号转换到的逻辑值的互补电压电平。

公开(公告)号：US5708386A

公开(公告)日：1998-01-13

申请号：US623583

申请日：1996-03-28

申请人： Hwang-Cherng Chow

发明人： Hwang-Cherng Chow

IPC分类号： H03K17/16

CPC分类号： H03K17/163

摘要： An output buffer is provided with a terminal, a first driver, a second driver and enable circuitry. The first driver is for driving the terminal to a voltage corresponding to a logic value of the output signal. The second driver is for driving the terminal to the same voltage as the first driver, when the output signal transitions in logic value. The enable circuitry responds to a transition in logic value of the output signal by, after a predetermined delay, enabling the second driver to drive the terminal. However, the enable circuitry only enables the second driver to drive the terminal for a predetermined time period.

摘要翻译： 输出缓冲器具有端子，第一驱动器，第二驱动器和使能电路。 第一驱动器用于将终端驱动到对应于输出信号的逻辑值的电压。 第二个驱动器是用于将终端驱动到与第一驱动器相同的电压，当输出信号转换为逻辑值时。 使能电路响应输出信号的逻辑值的转换，在预定的延迟之后使得第二驱动器能够驱动终端。 然而，使能电路仅使得第二驱动器能够在预定时间段内驱动终端。