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15 条记录 (耗时 0.012 秒)

    High and low speed output buffer with controlled slew rate
    1.
    发明授权
    High and low speed output buffer with controlled slew rate 失效
    高速和低速输出缓冲器，具有受控的转换速率

    公开(公告)号：US5850159A

    公开(公告)日：1998-12-15

    申请号：US854393

    申请日：1997-05-12

    申请人： Hwang-Cherng Chow ,  Chen-Yi Huang ,  Tain-Shun Wu

    发明人： Hwang-Cherng Chow ,  Chen-Yi Huang ,  Tain-Shun Wu

    IPC分类号： H03K19/003 ,  H03K17/296

    CPC分类号： H03K19/00361

    摘要： An output buffer is provided which receives an input signal for output onto an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage corresponding to a logic value of the input signal. The second driver has a higher driving capacity than the first driver. The output buffer also has control circuitry receiving a transition in logic value of the input signal and at least one mode signal. The control circuitry responds to the transition in logic value by delaying the second driver from driving the output terminal to a complementary voltage until after the first driver begins to drive the output terminal to the complementary voltage. In so doing, the control circuitry delays the second driver by a first delay, when the mode signal(s) indicates a full speed mode. On the other hand, the control circuitry delays the second driver by a second delay, that is longer than the first delay, when the mode signal(s) indicates a low speed mode.

    摘要翻译： 提供了输出缓冲器，其接收用于输出到输出端子的输入信号。 输出缓冲器具有用于将输出端驱动到对应于输入信号的逻辑值的电压的第一驱动器和第二驱动器。 第二个驾驶员的驾驶能力比第一个驾驶员高。 输出缓冲器还具有接收输入信号和至少一个模式信号的逻辑值转换的控制电路。 控制电路通过将第二驱动器从驱动输出端子延迟到互补电压来响应逻辑值的转换，直到第一驱动器开始将输出端驱动到互补电压为止。 这样做时，当模式信号指示全速模式时，控制电路将第二驱动器延迟第一延迟。 另一方面，当模式信号指示低速模式时，控制电路延迟第二驱动器比第一延迟长的第二延迟。

    High drive CMOS output buffer with fast and slow speed controls
    2.
    发明授权
    High drive CMOS output buffer with fast and slow speed controls 失效
    高驱动CMOS输出缓冲器，具有快速和慢速的速度控制

    公开(公告)号：US6094086A

    公开(公告)日：2000-07-25

    申请号：US855844

    申请日：1997-05-12

    申请人： Hwang-Cherng Chow

    发明人： Hwang-Cherng Chow

    IPC分类号： H03K17/16 ,  H03K17/296

    CPC分类号： H03K17/164

    摘要： An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The second driver has a greater (current) driving capacity than the first driver. The output buffer also has control circuitry which detects a transition in the logic value of the input signal. In response, the control circuitry generates a particular pulse aligned with the input signal logic value transition having a particular constant voltage level for a predetermined time period. Furthermore, the control circuitry delays the second circuit from driving the output terminal to a complementary voltage level corresponding to the logic value to which the input signal transitions during the predetermined time period.

    摘要翻译： 提供输出缓冲器，其接收输入信号并驱动输出端子。 输出缓冲器具有用于将输出端驱动到与输入信号的逻辑值对应的电压电平的第一驱动器和第二驱动器。 第二个驾驶员的驾驶能力比第一个驾驶员要大（目前）。 输出缓冲器还具有检测输入信号的逻辑值中的转换的控制电路。 作为响应，控制电路产生与预定时间段具有特定恒定电压电平的输入信号逻辑值转换对准的特定脉冲。 此外，控制电路延迟第二电路驱动输出端子到对应于在预定时间段期间输入信号转换到的逻辑值的互补电压电平。

    CMOS output buffer with reduced L-DI/DT noise
    3.
    发明授权
    CMOS output buffer with reduced L-DI/DT noise 失效
    CMOS输出缓冲器具有降低的L-DI / DT噪声

    公开(公告)号：US5708386A

    公开(公告)日：1998-01-13

    申请号：US623583

    申请日：1996-03-28

    申请人： Hwang-Cherng Chow

    发明人： Hwang-Cherng Chow

    IPC分类号： H03K17/16

    CPC分类号： H03K17/163

    摘要： An output buffer is provided with a terminal, a first driver, a second driver and enable circuitry. The first driver is for driving the terminal to a voltage corresponding to a logic value of the output signal. The second driver is for driving the terminal to the same voltage as the first driver, when the output signal transitions in logic value. The enable circuitry responds to a transition in logic value of the output signal by, after a predetermined delay, enabling the second driver to drive the terminal. However, the enable circuitry only enables the second driver to drive the terminal for a predetermined time period.

    摘要翻译： 输出缓冲器具有端子，第一驱动器，第二驱动器和使能电路。 第一驱动器用于将终端驱动到对应于输出信号的逻辑值的电压。 第二个驱动器是用于将终端驱动到与第一驱动器相同的电压，当输出信号转换为逻辑值时。 使能电路响应输出信号的逻辑值的转换，在预定的延迟之后使得第二驱动器能够驱动终端。 然而，使能电路仅使得第二驱动器能够在预定时间段内驱动终端。

    Duty cycle control buffer circuit with selective frequency dividing function
    6.
    发明授权
    Duty cycle control buffer circuit with selective frequency dividing function 失效
    具有选择性分频功能的占空比控制缓冲电路

    公开(公告)号：US6060922A

    公开(公告)日：2000-05-09

    申请号：US26842

    申请日：1998-02-20

    申请人： Hwang-Cherng Chow ,  Chi-Chang Shuai ,  Yuan-Hua Chu

    发明人： Hwang-Cherng Chow ,  Chi-Chang Shuai ,  Yuan-Hua Chu

    IPC分类号： H03K5/04 ,  H03K5/156 ,  H03K3/017

    CPC分类号： H03K5/04 ,  H03K5/1565

    摘要： A duty cycle control buffer uses an edge detector input stage to detect the transitions of an unpredictable clock signal input. The edge detector generates one shot output signals in synchronism with the clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses, at the same frequency as the original clock input. The rectangular pulses are inverted and then averaged, to provide a voltage input to one side of an operational amplifier. A reference voltage is supplied to the other side of the operational amplifier, such that the difference between the average voltage and the reference voltage generates an output control voltage from the operational amplifier. This control voltage provides negative feedback to a pulse width control stage within the monostable multivibrator, thereby adjusting the pulse width of the rectangular pulse output until a steady state is reached. A frequency divider circuit may be inserted in front of the edge detector to add a selective frequency dividing capability to the duty cycle control buffer.

    摘要翻译： 占空比控制缓冲器使用边沿检测器输入级来检测不可预测的时钟信号输入的转换。 边沿检测器产生与时钟信号同步的单触发输出信号。 脉冲宽度可调单稳态多谐振荡器将单触发信号转换成与原始时钟输入相同频率的矩形脉冲。 将矩形脉冲反相然后平均，以向运算放大器的一侧提供电压输入。 参考电压被提供给运算放大器的另一侧，使得平均电压和参考电压之间的差产生来自运算放大器的输出控制电压。 该控制电压向单稳态多谐振荡器内的脉冲宽度控制级提供负反馈，从而调整矩形脉冲输出的脉冲宽度，直到达到稳定状态。 可以在边缘检测器的前面插入分频器电路，以向占空比控制缓冲器增加选择性分频能力。

    CMOS bidirectional buffer for mixed voltage applications
    7.
    发明授权
    CMOS bidirectional buffer for mixed voltage applications 失效
    用于混合电压应用的CMOS双向缓冲器

    公开(公告)号：US5917348A

    公开(公告)日：1999-06-29

    申请号：US922469

    申请日：1997-09-02

    申请人： Hwang-Cherng Chow

    发明人： Hwang-Cherng Chow

    IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K3/00

    CPC分类号： H03K19/01714 ,  H03K19/01721 ,  H03K19/018592

    摘要： In a preferred embodiment of the present invention, a bidirectional buffer connects a first device, such as a CMOS chip having a first voltage, such as VCC, to a second device having a second voltage, such as VDD, through a terminal pad. The buffer includes a bootstrap capacitor to assist in driving up the terminal pad. In particular, the buffer comprises an output and an input portion. The output portion includes a first driver for driving the terminal pad up to VDD and a second driver for driving the terminal pad down to VSS. The first driver includes a pull-up PMOS transistor and a pull-up NMOS transistor connected in series and the second driver includes a pull-down NMOS transistor. Further, preferably one pair of push-pull bootstrap control transistors are connected in parallel to the gate of the pull-up NMOS transistor for quickly driving up the first driver to a voltage level based on the bootstrap capacitor having a predetermined capacitance. The input portion includes an invertor and a protection resistor for protecting the invertor from static charges.

    摘要翻译： 在本发明的优选实施例中，双向缓冲器通过端子焊盘将具有诸如VCC的第一电压的诸如CMOS芯片的第一器件连接到具有诸如VDD的第二电压的第二器件。 缓冲器包括一个自举电容器，以帮助驱动端子板。 特别地，缓冲器包括输出和输入部分。 输出部分包括用于驱动终端焊盘直到VDD的第一驱动器和用于将端子焊盘驱动到VSS的第二驱动器。 第一驱动器包括串联连接的上拉PMOS晶体管和上拉NMOS晶体管，第二驱动器包括下拉式NMOS晶体管。 此外，优选地，一对推挽自举控制晶体管并联连接到上拉NMOS晶体管的栅极，用于基于具有预定电容的自举电容快速将第一驱动器升高到电压电平。 输入部分包括反相器和保护电阻器，用于保护反相器免受静电荷的影响。

    CMOS level shifter with steady-state and transient drivers
    8.
    发明授权
    CMOS level shifter with steady-state and transient drivers 失效
    具有稳态和瞬态驱动器的CMOS电平转换器

    公开(公告)号：US5781026A

    公开(公告)日：1998-07-14

    申请号：US623310

    申请日：1996-03-28

    申请人： Hwang-Cherng Chow

    发明人： Hwang-Cherng Chow

    IPC分类号： H03K3/356 ,  H03K19/0185

    CPC分类号： H03K3/356147

    摘要： A level shifter is provided with first and second steady-state drivers and transient driver circuitry. Each steady-state driver includes a low enable input, a high enable input and an output. Each steady-state driver outputs from its respective output a low voltage level signal when an enabling voltage level is received at its low enable input and a disabling voltage is received at its high enable input. Furthermore, each steady-state driver outputs from its output a first high voltage level signal, that is higher than a second high voltage level of an input signal, when a disabling voltage level is received at its low enable input and an enabling high voltage level is received at its high enabling input. The high enable input of the first steady-state driver is connected to the output of the second steady-state driver. The high enable input of the second steady-state driver is connected to the output of the first steady-state driver. The input of the first steady-state driver receives a complement of the input signal and the input of the second steady-state driver receives the input signal. The transient driver circuitry responds to a transition in the voltage level of the input signal by driving the output of one of the first and second drivers, to the first high voltage level, for a certain time period. The transient driver circuitry is enabled to drive the output with a maximum driving capacity throughout the aforementioned certain time period.

    摘要翻译： 电平移位器具有第一和第二稳态驱动器和瞬态驱动器电路。 每个稳态驱动器包括低使能输入，高使能输入和输出。 当在其低使能输入端接收到使能电压电平时，每个稳态驱动器从其相应的输出端输出低电压电平信号，并在其高使能输入端接收禁止电压。 此外，当在其低使能输入处接收到禁用电压电平时，每个稳态驱动器从其输出端输出高于输入信号的第二高电压电平的第一高电压电平信号，以及使能高电平 在其高启用输入下被接收。 第一稳态驱动器的高使能输入连接到第二稳态驱动器的输出。 第二稳态驱动器的高使能输入连接到第一稳态驱动器的输出。 第一稳态驱动器的输入接收输入信号的补码，并且第二稳态驱动器的输入接收输入信号。 瞬态驱动器电路通过将第一和第二驱动器中的一个驱动器的输出驱动到第一高电压电压来响应输入信号的电压电平的转变一段时间。 瞬态驱动器电路能够在上述特定时间段内以最大驱动能力驱动输出。

    CMOS level shifting circuit
    9.
    发明授权
    CMOS level shifting circuit 失效
    CMOS电平移位电路

    公开(公告)号：US5698993A

    公开(公告)日：1997-12-16

    申请号：US623351

    申请日：1996-03-28

    申请人： Hwang-Cherng Chow

    发明人： Hwang-Cherng Chow

    IPC分类号： H03K3/356 ,  H03K19/0948 ,  H03K19/017

    CPC分类号： H03K3/356113

    摘要： A level shifting inverter is provided with first and second drivers which may be level shifting inverters, which each have a low enable input, a high enable input and an output. Each driver outputs a low voltage level or a second high voltage level(that is higher than a first high voltage level of an input signal) depending on enabling and disabling voltage levels received at the high and low enable inputs of each driver. The high enable input of the first and second drivers are connected in a cross-coupled feedback configuration. The input of the first driver receives a complement of the input signal whereas the input of the second driver receives the input signal. The level shifter also has transition driver circuitry. The transition driver circuitry has an input receiving the second high voltage level, a first biasing input receiving the input signal and a second biasing input receiving the complement of the input signal. The transition driver circuitry responds to an input signal voltage level transition by charging the output of a first one of the first and second drivers to approximately the second high voltage level and discharging, to the low voltage level, the output of a second one of the first and second drivers. The charging and discharging of the first and second driver outputs causes a disabling voltage level to be outputted to the high enable input of the first one of the first and second drivers and an enabling voltage level to be outputted to the high enable input of the second one of the first and second drivers.

    摘要翻译： 电平变换逆变器设置有第一和第二驱动器，其可以是电平转换逆变器，其各自具有低使能输入，高使能输入和输出。 每个驱动器根据启用和禁用在每个驱动器的高和低使能输入端接收的电压电平而输出低电压电平或第二高电压电平（高于输入信号的第一高电压电平）。 第一和第二驱动器的高使能输入以交叉耦合反馈配置连接。 第一驱动器的输入接收输入信号的补码，而第二驱动器的输入接收输入信号。 电平转换器还具有转换驱动器电路。 转换驱动器电路具有接收第二高电压电平的输入，接收输入信号的第一偏置输入和接收输入信号的补码的第二偏置输入。 转换驱动器电路通过将第一和第二驱动器中的第一驱动器的输出充电到大约第二高电压电平来响应输入信号电压电平转换，并将低电平电平的第二个的输出 第一和第二个司机。 第一和第二驱动器输出的充电和放电使得禁用电压电平被输出到第一和第二驱动器的第一驱动器的高使能输入，并且使能电压电平被输出到第二和第二驱动器的高使能输入 第一和第二个驱动程序之一。

    Frequency multiplication circuit
    10.
    发明授权
    Frequency multiplication circuit 有权
    倍频电路

    公开(公告)号：US06198317B1

    公开(公告)日：2001-03-06

    申请号：US09393232

    申请日：1999-09-09

    申请人： Hwang-Cherng Chow ,  Yuan-Hua Chu ,  Chi-Chang Shuai

    发明人： Hwang-Cherng Chow ,  Yuan-Hua Chu ,  Chi-Chang Shuai

    IPC分类号： H03B1900

    CPC分类号： H03K5/00006 ,  H03K3/0307 ,  H03K5/1565

    摘要： An N times frequency multiplication circuit uses duty cycle control buffers in combination with edge detectors to provide both multiplication and 50% duty cycle adjustment. Parallel branches of duty cycle control buffers are preset for respective duty cycles of 1/N, 2/N,...,N−1/N. The buffers each receive a common edge detected input signal and simultaneously output their respective duty cycle adjusted clock signals. A rising and falling edge detector generates a pulse train at double the frequency of the 1/N buffer output, while falling edge detectors generate time spaced pulse trains from the outputs of their respective 2/N,...,N−1/N buffers. These pulse trains are combined in an OR gate to provide an output pulse train at a frequency N times the input clock frequency fin. A final stage duty cycle control buffer adjusts the N times fin output signal to a 50% duty cycle.

    摘要翻译： N倍频电路使用与边缘检测器组合的占空比控制缓冲器来提供乘法和50％占空比调整。 1 / N，2 / N，...，N-1 / N的占空比的预置占空比控制缓冲器的并行分支。 每个缓冲器都接收公共边沿检测的输入信号，同时输出它们各自的占空比调整的时钟信号。 上升沿和下降沿检测器以1 / N缓冲器输出的频率的两倍产生脉冲串，而下降沿检测器从它们各自的2 / N，...，N-1 / N的输出产生时间间隔的脉冲串 缓冲区 这些脉冲串组合在或门中以提供输入脉冲序列，频率为输入时钟频率fin的N倍。 最后一级占空比控制缓冲器将N次散热片输出信号调整到50％占空比。